Xilinx Constraints Guide

IBUF_DELAY_VALUE (Input Buffer Delay Value)
The IBUF_DELAY_VALUE (Input Buffer Delay Value) constraint:
• Is a mapping constraint.
Architecture Support
Applicable Elements
• Adds additional static delay to the input path of the FPGA array.
Chapter 4: Xilinx Constraints
• Can be applied to any input or bi-directional signal that is not directly driving a
clock or IOB (Input Output Block) register.
For more information regarding the constraint of signals driving clock and IOB registers,
see IFD_DELAY_VALUE. IBUF_DELAY_VALUE can be set to an integer value from
0-16. The value 0 is the default value, and applies no additional delay to the input
path. A larger value correlates to a larger delay added to input path. These values do
not directly correlate to a unit of time but rather additional buffer delay. For more
information, see the device data sheets.
Applies to Spartan®-3A and Spartan-3E devices.
Any top-level I/O port.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Schematic Syntax
• Attach a new property to the top-level port of the schematic
• Attribute Name
IBUF_DELAY_VALUE
• Attribute Values
0-16
VHDL Syntax
Attach a VHDL attribute to the appropriate top-level port.
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of top_level_port_name: signal is "value";
a valid value is from 0 to 16.
The following statement assigns an IBUF_DELAY_VALUE increment of 5 to the net
DataIn1
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of DataIn1: label is "5";
For more information about basic VHDL syntax, see VHDL Attributes.
Constraints Guide
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