Xilinx Constraints Guide

LOC Range Constraint Examples
Constraint Description
INST “instance_name “
LOC=SLICE_X3Y5:SLICE_X5Y20;
Chapter 4: Xilinx Constraints
FPGA Place logic in any slice within
the rectangular area bounded by
SLICE_X3Y5 (the lower left corner) and
SLICE_X5Y20 (the upper right corner)
on the XY SLICE grid.
LOC ranges can be supplemented with the keyword SOFT. Unlike AREA_GROUP, LOC
ranges do not influence the packing of symbols. LOC range is strictly a placement
constraint used by PAR.
Following is the LOC syntax for CPLD devices:
INST “instance_name” LOC=pin_name;
or
INST “ instance_name” LOC=FBff ;
or
INST “instance_name” LOC=FB ff_mm;
where
• pin_name is Pnn for numeric pin names or rc for row-column pin names
• ff is a function block number
• mm is a macrocell number within a function block
The two constraint formats for FBff and FBff_mm are only applicable for outputs and
bidirectional pins, not for inputs.
The first constraint format:
INST “instance_name” LOC=pin_name;
is applicable for all types of IO.
Syntax Examples
For examples of legal placement constraints for each type of logic element in FPGA
designs, see Syntax for FPGA Devices for this constraint, and the Relative Location
(RLOC) constraint. Logic elements include flip-flops, ROMs and RAMs, block RAMS,
FMAPs, BUFTs, CLBs, IOBs, I/Os, edge decoders, and global buffers.
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Schematic Syntax
• Attach to an instance
• Attribute Name: LOC
• Attribute Values: value
For valid values, see Syntax for FPGA Devices and Syntax for CPLD Devices for this
constraint.
VHDL Syntax
Declare the VHDL constraint as follows:
attribute loc: string;
Specify the VHDL constraint as follows:
Constraints Guide
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