Xilinx Constraints Guide

Timing Constraint Strategies
Chapter 3
The goal of using timing constraints is to ensure that all the design requirements are
communicated to the implementation tools. This goal also implies that all paths are
covered by the appropriate constraint. This chapter provides general guidelines that
explain the strategy for identifying and constraining the most common timing paths
in FPGA devices in the most efficient manner possible.
Note For more information, see the Timing Constraints User Guide (UG612)..
Basic Constraints Methodology
In order to ensure a valid design, the timing requirements for all paths must be
communicated to the implementation software. The timing requirements can be broken
down into several global categories based on the type of path that is to be covered. The
most common types of path categories include:
• Input paths
• Register-to-register paths
• Output paths
• Path specific exceptions
A Xilinx® timing constraint is associated with each of these global category types. The
most efficient way to specify these constraints is to begin with global constraints, then
add path specific exceptions as needed. In many cases, only the global constraints are
required.
The FPGA implementation software is driven by the specified timing requirements.
The software assigns device resources, and expends the appropriate amount of effort
necessary to ensure that the timing requirements are met. However, when a requirement
is over-constrained (or specified as a value greater than the design requirement), the
effort to meet this constraint increases significantly, and results in increased memory
use and tool runtime. In addition, over-constraining can degrade performance for not
only that particular constraint, but for other constraints as well. For this reason, Xilinx
recommends that you specify the constraint values using the actual design requirements.
The method of applying constraints given in this guide uses User Constraints File (UCF)
constraint syntax examples. This format highlights the constraints syntax that conveys
the design requirements. However, the easiest way to enter design constraints is to
use Constraints Editor, which:
• Provides a unified location in which to manage all timing constraints associated
with a design
• Provides assistance in creating timing constraints from the design requirements
Constraints Guide
UG625 (v. 13.2) July 6, 2011 www.xilinx.com 51