Xilinx Constraints Guide

Schematic LOC=P17
Chapter 4: Xilinx Constraints
UCF INST “/top-102/data0_pad” LOC=P17;
Place the I/O in the IOB at pin 17. For pin grid arrays, a pin name such as B3 or T1 is used.
IOB Constraint Examples
You can assign I/O pads, buffers, and registers to an individual IOB location. IOB
locations are identified by the corresponding package pin designation.
The following examples illustrate the format of IOB constraints. Specify LOC= and the
pin location. If the target symbol represents a soft macro containing only I/O elements,
for example, INFF8, the LOC constraint is applied to all I/O elements contained in that
macro. If the indicated I/O elements do not fit into the specified locations, an error
is generated.
The following UCF statement places the I/O element in location P13. For PGA packages,
the letter-number designation is used, for example, B3.
INST “ instance_name” LOC=P13;
You can prohibit the mapper from using a specific IOB. You might take this step to
keep user I/O signals away from semi-dedicated configuration pins. Such PROHIBIT
constraints can be assigned only through the UCF file.
IOBs are prohibited by specifying a PROHIBIT constraint preceded by the CONFIG
keyword, as shown in the following example.
Schematic None
UCF CONFIG PROHIBIT=p36, p37, p41;
Do not place user I/Os in the IOBs at pins 36, 37, or 41. For pin grid arrays, pin names
such as D14, C16, or H15 are used.
Mapping Constraint Examples (FMAP)
Mapping constraints control the mapping of logic into CLBs. They have two parts.
The first part is an FMAP component placed on the schematic. The second is a LOC
constraint that can be placed on the schematic or in the constraints file.
FMAP controls the mapping of logic into function generators. This symbol does not
define logic on the schematic; instead, it specifies how portions of logic shown elsewhere
on the schematic should be mapped into a function generator.
The FMAP symbol defines mapping into a four-input (F) function generator.
For the FMAP symbol as with the CLBMAP primitive, MAP=PUC or PUO is supported,
as well as the LOC constraint. (Currently, pin locking is not supported. MAP=PLC or
PLO is translated into PUC and PUO, respectively.)
Example One
Place the FMAP symbol in the SLICE at row 7, column 3.
Schematic LOC=SLICE_X7Y3
UCF INST “$1I323”LOC=SLICE_X2Y4,
SLICE_X3Y4;
Example Two
Place the FMAP symbol in either the SLICE at row 2, column 4 or the SLICE at row 3,
column 4.
Constraints Guide
UG625 (v. 13.2) July 6, 2011 www.xilinx.com 165