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Xilinx Constraints Guide

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BLKNM (Block Name)<br />

Architecture Support<br />

Applicable Elements<br />

The BLKNM (Block Name) constraint:<br />

• Is an advanced mapping constraint<br />

• Assigns block names to qualifying primitives and logic elements.<br />

Chapter 4: <strong>Xilinx</strong> <strong>Constraints</strong><br />

If the same BLKNM constraint is assigned to more than one instance, the software<br />

attempts to map them into the same block. Conversely, two symbols with different<br />

BLKNM names are not mapped into the same block. Placing similar BLKNM constraints<br />

on instances that do not fit within one block causes an error.<br />

Specifying identical BLKNM constraints on FMAP tells the software to group the<br />

associated function generators into a single SLICE. Using BLKNM, you can partition a<br />

complete SLICE without constraining the SLICE to a physical location on the device.<br />

BLKNM constraints, like LOC constraints, are specified from the design. Since<br />

hierarchical paths are not prefixed to BLKNM constraints, BLKNM constraints for<br />

different SLICEs must be unique throughout the entire design. For information on<br />

attaching hierarchy to block names, see Hierarchical Block Name (HBLKNM).<br />

BLKNM allows any elements except those with a different BLKNM to be mapped<br />

into the same physical component. Elements without a BLKNM can be packed with<br />

those that have a BLKNM. For information on allowing only elements with the same<br />

XBLKNM to be mapped into the same physical component, see XBLKNM.<br />

Applies to FPGA devices. Does not apply to CPLD devices.<br />

This constraint may be used with an FPGA device in one or more of the following design<br />

elements, or categories of design elements. Not all devices support all elements. To see<br />

which design elements can be used with which devices, see the Libraries <strong>Guide</strong>s. For<br />

more information, see the device data sheet.<br />

• Flip-flop and latch primitives<br />

• Any I/O element or pad<br />

• FMAP<br />

• ROM primitives<br />

• RAMS and RAMD primitives<br />

• Carry logic primitives<br />

• Block RAM<br />

Propagation Rules<br />

You can also attach BLKNM to the net connected to the pad component in a User<br />

<strong>Constraints</strong> File (UCF) file. NGDBuild transfers the constraint from the net to the pad<br />

instance in the NGD file so that it can be processed by the mapper. Use the following<br />

syntax:<br />

NET “net_name” BLKNM=property_value;<br />

When attached to a design element, this constraint is propagated to all applicable<br />

elements in the hierarchy within the design element.<br />

<strong>Constraints</strong> <strong>Guide</strong><br />

UG625 (v. 13.2) July 6, 2011 www.xilinx.com 79

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