Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
NOREDUCE (No Reduce)
Architecture Support
Applicable Elements
Propagation Rules
The NOREDUCE (No Reduce) constraint:
• Is a fitter and synthesis constraint.
• Prevents minimization of redundant logic terms that are typically included in a
design to avoid logic hazards or race conditions.
• Identifies the output node of a combinatorial feedback loop to ensure correct
mapping.
When constructing combinatorial feedback latches in a design, always apply
NOREDUCE to the latch’s output net and include redundant logic terms when necessary
to avoid race conditions.
Applies to CPLD devices only. Does not apply to FPGA devices.
Applies to the net to which it is attached.
This constraint is a net constraint. Any attachment to a design element is illegal.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Schematic Syntax
• Attach to a net
• Attribute Name
NOREDUCE
• Attribute Values
– TRUE
– FALSE
VHDL Syntax
Declare the VHDL constraint as follows:
attribute NOREDUCE: string;
Specify the VHDL constraint as follows:
attribute NOREDUCE of signal_name: signal is “{TRUE|FALSE}”;
For more information about basic VHDL syntax, see VHDL Attributes.
Verilog Syntax
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* NOREDUCE = “{TRUE|FALSE}” *)
For more information about basic Verilog syntax, see Verilog Attributes.
Constraints Guide
192 www.xilinx.com UG625 (v. 13.2) July 6, 2011