Xilinx Constraints Guide

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Chapter 4: Xilinx Constraints FSM_STYLE (FSM Style) For information about the FSM_STYLE (FSM Style) constraint, see the XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices (UG687). Constraints Guide 124 www.xilinx.com UG625 (v. 13.2) July 6, 2011
HBLKNM (Hierarchical Block Name) Architecture Support Applicable Elements The HBLKNM (Hierarchical Block Name) constraint: • Is an advanced mapping constraint. Chapter 4: Xilinx Constraints • Assigns hierarchical block names to logic elements and controls grouping in a flattened hierarchical design. When elements on different levels of a hierarchical design carry the same block name, and the design is flattened, NGCBuild prefixes a hierarchical path name to the HBLKNM value. Like Block Name, HBLKNM forces function generators and flip-flops into the same CLB. Symbols with the same HBLKNM constraint map into the same CLB, if possible. However, using HBLKNM instead of Block Name has the advantage of adding hierarchy path names during translation, and therefore the same HBLKNM constraint and value can be used on elements within different instances of the same design element. Applies to FPGA devices. Does not apply to CPLD devices. HBLKNM may be used with an FPGA device in one or more of the following design elements, or categories of design elements. Not all devices support all elements. To see which design elements can be used with which device families, see the Xilinx® Libraries Guides for details. For more information, see the device data sheet. • Registers • I/O elements and pads • FMAP • PULLUP • ACLK • GCLK • BUFG • BUFGS • BUFGP • ROM • RAMS • RAMD Propagation Rules • Carry logic primitives You can also attach HBLKNM to the net connected to the pad component in a UCF file. NGCBuild transfers the constraint from the net to the pad instance in the NGD file so that it can be processed by the mapper. Use the following syntax: NET “net_name” HBLKNM=property_value; When attached to a design element, HBLKNM is propagated to all applicable elements in the hierarchy within the design element. However, when attached to a NET, HBLKNM is only propagated to PADs. Constraints Guide UG625 (v. 13.2) July 6, 2011 www.xilinx.com 125
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Constraints Guide UG625 (v. 13.2) J
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Table of Contents Revision History
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IBUF_DELAY_VALUE (Input Buffer Dela
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Constraint Types Attributes and Con
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Grouping Constraints for Timing Cha
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The name qualifier can include the
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Physical Constraints Mapping Note T
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Placement Constraints Chapter 1: Co
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Routing Directives Routing directiv
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Timing Constraints Chapter 1: Const
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UCF Timing Constraint Support From-
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Timing Model Constraint Priority Ch
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Chapter 2 Entry Strategies for Xili
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Constraint Schematic VHDL Verilog L
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An attribute can be declared in an
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User Constraints File (UCF) UCF Flo
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Syntax Chapter 2: Entry Strategies
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Entering Multiple Constraints File
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Chapter 2: Entry Strategies for Xil
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Running Constraints Editor As a Sta
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Defining I/O Pin Configurations Cha
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Placement LOC Constraint Assignment
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Verilog Example -------------module
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Chapter 2: Entry Strategies for Xil
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Timing Specification Priorities Cha
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Timing Constraint Strategies Chapte
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Chapter 3: Timing Constraint Strate
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The global OFFSET IN constraint for
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The PERIOD constraint syntax for th
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Example Chapter 3: Timing Constrain
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Chapter 3: Timing Constraint Strate
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The global OFFSET OUT constraints f
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Multi-Cycle Paths Chapter 3: Timing
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Xilinx Constraints Each Xilinx® co
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RANGE Chapter 4: Xilinx Constraints
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Chapter 4: Xilinx Constraints Range
Page 73 and 74: COMPRESSION GROUP PLACE Chapter 4:
Page 75 and 76: Defining From Timing Groups Chapter
Page 77 and 78: BEL (BEL) The BEL (BEL) constraint:
Page 79 and 80: BLKNM (Block Name) Architecture Sup
Page 81 and 82: BUFG (BUFG) The BUFG (BUFG) constra
Page 83 and 84: Clock Dedicated Route (CLOCK_DEDICA
Page 85 and 86: COMPGRP (Component Group) Architect
Page 87 and 88: • S_SELECTMAP16 Slave SelectMAP M
Page 89 and 90: Verilog Syntax Chapter 4: Xilinx Co
Page 93 and 94: PCF Syntax CONFIG DCI_CASCADE = ",
Page 95 and 96: Default (DEFAULT) Chapter 4: Xilinx
Page 97 and 98: Example (* KEEPER = “TRUE” *) D
Page 99 and 100: DIFF_TERM (Diff_Term) Architecture
Page 101 and 102: DIRECTED_ROUTING (Directed Routing)
Page 103 and 104: DISABLE (Disable) The DISABLE (Disa
Page 105 and 106: DRIVE (Drive) The DRIVE (Drive) con
Page 107 and 108: XCF Syntax MODEL “entity_name”
Page 109 and 110: ENABLE (Enable) The ENABLE (Enable)
Page 111 and 112: ENABLE_SUSPEND (Enable Suspend) Arc
Page 115 and 116: Constraints Editor Syntax Chapter 4
Page 117 and 118: VHDL Syntax Declare the VHDL constr
Page 119 and 120: UCF and NCF Syntax NET “signal_na
Page 121 and 122: Chapter 4: Xilinx Constraints You a
Page 123: Constraints Editor Syntax Chapter 4
Page 127 and 128: HIODELAY_GROUP (HIODELAY Group) Arc
Page 129 and 130: VHDL Syntax Declare the VHDL constr
Page 131 and 132: HU_SET (HU Set) The HU_SET (HU Set)
Page 133 and 134: IBUF_DELAY_VALUE (Input Buffer Dela
Page 135 and 136: IFD_DELAY_VALUE (IFD Delay Value) T
Page 137 and 138: IN_TERM (In Term) Architecture Supp
Page 139 and 140: INREG (Input Registers) Architectur
Page 141 and 142: IOB (IOB) The IOB constraint: • I
Page 143 and 144: IOBDELAY (Input Output Block Delay)
Page 145 and 146: IODELAY_GROUP (IODELAY Group) Limit
Page 147 and 148: IOSTANDARD (Input Output Standard)
Page 149 and 150: Pinout and Area Constraints Editor
Page 153 and 154: Architecture Support Applicable Ele
Page 155 and 156: Keeper (KEEPER) Architecture Suppor
Page 157 and 158: LOC (Location) The LOC (Location) c
Page 159 and 160: Chapter 4: Xilinx Constraints The w
Page 161 and 162: LOC Range Constraint Examples Const
Page 163 and 164: PlanAhead Syntax Chapter 4: Xilinx
Page 165 and 166: Schematic LOC=P17 Chapter 4: Xilinx
Page 167 and 168: Example One Chapter 4: Xilinx Const
Page 169 and 170: Slices Prohibited Example Two Chapt
Page 171 and 172: LOCK_PINS (Lock Pins) Architecture
Page 173 and 174: where value is any chosen name unde
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MAP (Map) Architecture Support Appl
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Specify the Verilog constraint as f
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Architecture Support Applicable Ele
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MAXDELAY (Maximum Delay) Architectu
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PCF Syntax item MAXDELAY = maxvalue
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MAXSKEW (Maximum Skew) The MAXSKEW
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FPGA Editor Syntax Chapter 4: Xilin
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MIODELAY_GROUP (MIODELAY Group) Arc
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VHDL Syntax Declare the VHDL constr
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UCF and NCF Syntax Chapter 4: Xilin
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where Chapter 4: Xilinx Constraints
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Falling Edge Constraints Chapter 4:
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PlanAhead Syntax Chapter 4: Xilinx
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where Chapter 4: Xilinx Constraints
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UCF Syntax NET “clock” TNM_NET
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Verilog Syntax Chapter 4: Xilinx Co
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Attribute OUT_TERM: string; Specify
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TIMESPEC PERIOD Method Chapter 4: X
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Examples of a Primary Clock with De
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where • period is the required cl
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New PERIOD Specifications Output Pi
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Post CRC (POST_CRC) Architecture Su
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Post CRC Frequency (POST_CRC_FREQ)
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Post CRC Signal (POST_CRC_SIGNAL) A
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PRIORITY (Priority) Architecture Su
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The following are not supported: Ch
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PULLDOWN (Pulldown) Architecture Su
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PULLUP (Pullup) Architecture Suppor
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PWR_MODE (Power Mode) Architecture
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REG (Registers) The REG (Registers)
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RLOC (Relative Location) The Relati
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RLOC = X3Y4 Chapter 4: Xilinx Const
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Linking Sets Set Linkage Chapter 4:
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Chapter 4: Xilinx Constraints by th
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Linking Two HU_SET Sets Chapter 4:
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Specify the VHDL constraint as foll
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Chapter 4: Xilinx Constraints Diffe
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H_SET (H Set) Chapter 4: Xilinx Con
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Chapter 4: Xilinx Constraints The n
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Syntax Examples Chapter 4: Xilinx C
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RLOC_RANGE (Relative Location Range
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where the relative X values (m1 and
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UCF and NCF Syntax NET “mysignal
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VHDL Syntax Chapter 4: Xilinx Const
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SLOW (Slow) The SLOW (Slow) constra
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STEPPING (Stepping) Architecture Su
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VHDL Syntax Chapter 4: Xilinx Const
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Constraints Editor Syntax Chapter 4
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Chapter 4: Xilinx Constraints The f
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TIMEGRP (Timing Group) The TIMEGRP
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Defining Latch Subgroups by Gate Se
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Chapter 4: Xilinx Constraints When
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PCF Syntax TIMEGRP name; TIMEGRP na
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Separators FROM-TO Syntax TIMESPEC
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TNM (Timing Name) Chapter 4: Xilinx
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Chapter 4: Xilinx Constraints A qua
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TNM_NET (Timing Name Net) The TNM_N
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Schematic Syntax • Attach to a ne
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TPSYNC (Timing Point Synchronizatio
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UCF and NCF Syntax NET “net_name
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Using TPTHRU in a FROM TO Constrain
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TSidentifier (Timing Specification
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Ignoring Paths Note This form is no
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Chapter 4: Xilinx Constraints If yo
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Use Low Skew Lines (USELOWSKEWLINES
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VCCAUX (VCCAUX) Architecture Suppor
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VREF (VREF) The VREF (VREF) constra
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XBLKNM (XBLKNM) Architecture Suppor
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Additional Resources Appendix • X
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