Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
Verilog Syntax
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* USELOWSKEWLINES = “{YES|NO|TRUE|FALSE}” *)
For more information about basic Verilog syntax, see Verilog Attributes.
UCF and NCF Syntax
This statement forces net $1I87/1N6745 to be routed on one of the device’s low skew
resources.
NET “$1I87/$1N6745” USELOWSKEWLINES;
XCF Syntax
BEGIN MODEL “entity_name”
NET “signal_name” uselowskewlines={yes|true};
END;
Constraints Editor Syntax
For information on setting constraints in Constraints Editor, including syntax, see the
Constraints Editor Help.
PCF Syntax
Same as UCF and NCF Syntax above.
Constraints Guide
316 www.xilinx.com UG625 (v. 13.2) July 6, 2011