Xilinx Constraints Guide

MAP (Map)
Architecture Support
Applicable Elements
Chapter 4: Xilinx Constraints
MAP (Map) is an advanced mapping constraint. Place MAP on an FMAP to specify
whether pin swapping and the merging of other functions with the logic in the map are
allowed. If merging with other functions is allowed, other logic can also be placed
within the CLB, if space allows.
Applies to FPGA devices. Does not apply to CPLD devices.
FMAP
Propagation Rules
Applies to the design element to which it is attached
Syntax
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
UCF and NCF Syntax
INST “ instance_name” MAP=[PUC | PUO | PLC | PLO] ;
where
• PUC
The CLB pins are unlocked (U) and the CLB is closed (C). The software can swap
signals among the pins on the CLB, but cannot add or remove logic from the CLB.
• PUO (default)
The CLB pins are unlocked (U) and the CLB is open (O). The software can swap
signals among the pins on the CLB, and can add or remove logic from the CLB.
• PLC
The CLB pins are locked (L) and the CLB is closed (C). The software cannot swap
signals among the pins on the CLB, and cannot add or remove logic from the CLB.
• PLO
The CLB pins are locked (L) and the CLB is open (O). The software cannot swap
signals among the pins on the CLB, but can add or remove logic from the CLB.
Currently, only PUC and PUO are observed. PLC and PLO are translated into PUC
and PUO, respectively.
The following statement allows pin swapping, and ensures that no logic other than that
defined by the original map is mapped into the function generators.
INST “$1I3245/map_of_the_world” map=puc;
Constraints Guide
UG625 (v. 13.2) July 6, 2011 www.xilinx.com 175