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Xilinx Constraints Guide

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Chapter 4: <strong>Xilinx</strong> <strong>Constraints</strong><br />

VHDL Syntax<br />

Declare the VHDL constraint as follows:<br />

attribute drive: string;<br />

Specify the VHDL constraint as follows:<br />

attribute drive of {component_name |entity_name|label_name} : {component|entity<br />

|label} is “value”;<br />

For a list of the constraint values, see the UCF and NCF Syntax section below.<br />

For more information about basic VHDL syntax, see VHDL Attributes.<br />

Verilog Syntax<br />

Place the Verilog constraint immediately before the module or instantiation.<br />

Specify the Verilog constraint as follows:<br />

(* DRIVE = “value” *)<br />

For a list of the constraint values, see the UCF and NCF Syntax section below.<br />

For more information about basic Verilog syntax, see Verilog Attributes.<br />

UCF and NCF Syntax<br />

This section gives UCF and NCF Syntax examples for the following:<br />

• IOB Output Components (UCF)<br />

• SelectIO Technology Output Components<br />

IOB Output Components (UCF)<br />

For Spartan®-3 and higher devices or Virtex®-4 and higher devices:<br />

INST “instance_name” DRIVE={2|4|6| 8|12|16 |24};<br />

12 mA is the default<br />

SelectIO Technology Output Components<br />

This section applies to the following components:<br />

• IOBUF_SelectIO<br />

• OBUF_SelectIO<br />

• OBUFT_SelectIO<br />

The following table shows syntax examples for the named standard with Spartan-3<br />

devices and higher or Virtex-4 devices and higher. The default in each case is 12 mA.<br />

Standard Syntax<br />

LVTTL INST “instance_name” DRIVE={2|4|6|8|12|16|24};<br />

LVCMOS12<br />

LVCMOS15<br />

LVCMOS18<br />

LVCMOS25<br />

LVCMOS33<br />

INST “instance_name” DRIVE={2|4|6|8|12|16};<br />

INST “instance_name” DRIVE={2|4|6|8|12|16|24};<br />

<strong>Constraints</strong> <strong>Guide</strong><br />

106 www.xilinx.com UG625 (v. 13.2) July 6, 2011

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