Xilinx Constraints Guide

VHDL Syntax
Chapter 4: Xilinx Constraints
Before using SLEW, declare it with the following syntax placed after the architecture
declaration, but before the begin statement in the top-level VHDL file:
attribute SLEW: string;
Specify the VHDL constraint as follows:
attribute SLEW of {top_level_port_name}: signal is " value";
VHDL Syntax Example
entity top is
port (FAST_OUT: out std_logic);
end top;
architecture MY_DESIGN of top is
attribute SLEW: string;
attribute SLEW of FAST_OUT: signal is "FAST";
begin
For more information on basic VHDL syntax, see VHDL Attributes.
Verilog Syntax
Place the following attribute specification before the port declaration in the top-level
Verilog code:
(* SLEW="value" *)
Verilog Syntax Example
module top (
(* SLEW="FAST" *) output FAST_OUT
);
For more information about basic Verilog syntax, see Verilog Attributes.
User Constraints File (UCF) and Netlist Constraints File (NCF) Syntax
Placed on output or bi-directional port:
NET "top_level_port_name" SLEW="value";
UCF and NCF Syntax Example
NET "FAST_OUT" SLEW="FAST";
PlanAhead Syntax
For more information about using the PlanAhead software to create constraints, see
Floorplanning the Design in the PlanAhead User Guide (UG632). See PlanAhead in this
Guide for information about:
• Defining placement constraints
• Assigning placement constraints
• Defining I/O pin configurations
• Floorplanning and placement constraints
Constraints Guide
UG625 (v. 13.2) July 6, 2011 www.xilinx.com 265