Xilinx Constraints Guide

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Chapter 2: Entry Strategies for Xilinx Constraints XST Constraint File (XCF) Constraint Priority File Priorities XST constraints can be specified in the XST Constraint File (XCF). The XCF has an extension of .xcf. For more information, see: • ISE® Design Suite Help • XST Constraint File (XCF) section in the XST User Guide for Virtex-4, Virtex-5, Spartan-3, and Newer CPLD Devices In some cases more than one timing constraint covers the same path. The constraint conflict must be resolved, with the higher priority constraint taking precedence and being applied to the path, and the lower priority constraints being ignored for that path. The method of constraints resolution depends on both the order of constraint specification as well as the priority of the constraints specified. The rules of constraint priority resolution are described below. This determination is based upon the constraint prioritization or which constraint appears later in the Physical Constraints File (PCF), if there are overlapping constraints of the same priority. For example, if the design has two Period (PERIOD) constraints that cover the same paths, the later Period (PERIOD) constraint in the PCF file covers or analyzes these paths. The previous Period (PERIOD) constraints have “0 items analyzed” in the timing report. In order to modify the default constraint resolution behavior, the constraint priority can be assigned using the PRIORITY keyword. When conflicting constraints have the same priority, the order of specification is used to determine the constraint that takes precedence. The resolution rule for identical priority constraints is the constraint that is specified last overwrites any previously defined constraints. This rule applies to constraints within a single User Constraints File (UCF) as well as constraints defined in multiple UCF files. The following list defines the precedence order of identical priority constraints when these constraints are defined in different constraint files. The list is given in descending priority order with the highest priority constraint listed first. • Constraints in a Physical Constraints File (PCF) • Constraints in a User Constraints File (UCF) • Constraints in a Netlist Constraints File (NCF) • Attributes in a schematic or Constraints specified in HDL that are passed down in the netlist Constraints Guide 48 www.xilinx.com UG625 (v. 13.2) July 6, 2011
Timing Specification Priorities Chapter 2: Entry Strategies for Xilinx Constraints When two different constraints cover the same path, the constraint with the highest priority takes precedence and is applied to that path. Other constraints are ignored. Constraint priority is as follows, in descending order from highest to lowest. • Timing Ignore (TIG) • From Thru To (FROM-THRU-TO) – Source and Destination are User Defined Groups – Source or Destination are User Defined Groups – Source and Destination are Predefined Groups • From To (FROM-TO) – Source and Destination are User Defined Groups – Source or Destination are User Defined Groups – Source and Destination are Predefined Groups • OFFSET IN (Offset In) and OFFSET OUT (Offset Out) – Specific Data IOB (NET OFFSET) Constraint – Time Group of Data IOBs (Grouped OFFSET) Constraint – All Data IOBs (Global OFFSET) Constraint • Period (PERIOD) OFFSET Priorities If two specific OFFSET constraints at the same level of precedence cover the same path, an OFFSET with a register qualifier takes precedence over an OFFSET without a qualifier; if otherwise equivalent, the latter in the constraint file takes precedence. MAXSKEW and MAXDELAY Priorities Net delay and net skew specifications are analyzed independently of path delay analysis and do not interfere with one another. NET TIG do interact with the NET constraints and take precedence. Constraint Priority Exceptions Use Priority (PRIORITY) to override the default constraint resolution behavior. Priority (PRIORITY) uses a value of —255 to +255 to manually assign a priority to a constraint. The smaller the constraint value, the higher the constraint priority. This keyword affects constraint resolution priority only, and does not influence the priority in which the implementation tools Place and Route the resources covered by the constraint. For more information, see Priority (PRIORITY). Constraint Set Interaction There are circumstances in which constraint priority may not operate as expected. These cases include supersets, subsets, and intersecting sets of constraints. See the following figure. Constraints Guide UG625 (v. 13.2) July 6, 2011 www.xilinx.com 49
Page 1 and 2: Constraints Guide UG625 (v. 13.2) J
Page 3 and 4: Table of Contents Revision History
Page 5 and 6: IBUF_DELAY_VALUE (Input Buffer Dela
Page 7 and 8: Constraint Types Attributes and Con
Page 9 and 10: Grouping Constraints for Timing Cha
Page 11 and 12: The name qualifier can include the
Page 13 and 14: Physical Constraints Mapping Note T
Page 15 and 16: Placement Constraints Chapter 1: Co
Page 17 and 18: Routing Directives Routing directiv
Page 19 and 20: Timing Constraints Chapter 1: Const
Page 21 and 22: UCF Timing Constraint Support From-
Page 23 and 24: Timing Model Constraint Priority Ch
Page 25 and 26: Chapter 2 Entry Strategies for Xili
Page 27 and 28: Constraint Schematic VHDL Verilog L
Page 29 and 30: An attribute can be declared in an
Page 31 and 32: User Constraints File (UCF) UCF Flo
Page 33 and 34: Syntax Chapter 2: Entry Strategies
Page 35 and 36: Entering Multiple Constraints File
Page 37 and 38: Chapter 2: Entry Strategies for Xil
Page 39 and 40: Running Constraints Editor As a Sta
Page 41 and 42: Defining I/O Pin Configurations Cha
Page 43 and 44: Placement LOC Constraint Assignment
Page 45 and 46: Verilog Example -------------module
Page 47: Chapter 2: Entry Strategies for Xil
Page 51 and 52: Timing Constraint Strategies Chapte
Page 53 and 54: Chapter 3: Timing Constraint Strate
Page 55 and 56: The global OFFSET IN constraint for
Page 57 and 58: The PERIOD constraint syntax for th
Page 59 and 60: Example Chapter 3: Timing Constrain
Page 61 and 62: Chapter 3: Timing Constraint Strate
Page 63 and 64: The global OFFSET OUT constraints f
Page 65 and 66: Multi-Cycle Paths Chapter 3: Timing
Page 67 and 68: Xilinx Constraints Each Xilinx® co
Page 69 and 70: RANGE Chapter 4: Xilinx Constraints
Page 71 and 72: Chapter 4: Xilinx Constraints Range
Page 73 and 74: COMPRESSION GROUP PLACE Chapter 4:
Page 75 and 76: Defining From Timing Groups Chapter
Page 77 and 78: BEL (BEL) The BEL (BEL) constraint:
Page 79 and 80: BLKNM (Block Name) Architecture Sup
Page 81 and 82: BUFG (BUFG) The BUFG (BUFG) constra
Page 83 and 84: Clock Dedicated Route (CLOCK_DEDICA
Page 85 and 86: COMPGRP (Component Group) Architect
Page 87 and 88: • S_SELECTMAP16 Slave SelectMAP M
Page 89 and 90: Verilog Syntax Chapter 4: Xilinx Co
Page 91 and 92: Verilog Syntax Chapter 4: Xilinx Co
Page 93 and 94: PCF Syntax CONFIG DCI_CASCADE = ",
Page 95 and 96: Default (DEFAULT) Chapter 4: Xilinx
Page 97 and 98: Example (* KEEPER = “TRUE” *) D
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DIFF_TERM (Diff_Term) Architecture
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DIRECTED_ROUTING (Directed Routing)
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DISABLE (Disable) The DISABLE (Disa
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DRIVE (Drive) The DRIVE (Drive) con
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XCF Syntax MODEL “entity_name”
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ENABLE (Enable) The ENABLE (Enable)
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ENABLE_SUSPEND (Enable Suspend) Arc
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Verilog Syntax Chapter 4: Xilinx Co
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Constraints Editor Syntax Chapter 4
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VHDL Syntax Declare the VHDL constr
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UCF and NCF Syntax NET “signal_na
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Chapter 4: Xilinx Constraints You a
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HBLKNM (Hierarchical Block Name) Ar
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HIODELAY_GROUP (HIODELAY Group) Arc
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HU_SET (HU Set) The HU_SET (HU Set)
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IBUF_DELAY_VALUE (Input Buffer Dela
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IFD_DELAY_VALUE (IFD Delay Value) T
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IN_TERM (In Term) Architecture Supp
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INREG (Input Registers) Architectur
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IOB (IOB) The IOB constraint: • I
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IOBDELAY (Input Output Block Delay)
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IODELAY_GROUP (IODELAY Group) Limit
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IOSTANDARD (Input Output Standard)
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Pinout and Area Constraints Editor
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Architecture Support Applicable Ele
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Keeper (KEEPER) Architecture Suppor
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LOC (Location) The LOC (Location) c
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Chapter 4: Xilinx Constraints The w
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LOC Range Constraint Examples Const
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PlanAhead Syntax Chapter 4: Xilinx
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Schematic LOC=P17 Chapter 4: Xilinx
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Example One Chapter 4: Xilinx Const
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Slices Prohibited Example Two Chapt
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LOCK_PINS (Lock Pins) Architecture
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where value is any chosen name unde
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MAP (Map) Architecture Support Appl
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Specify the Verilog constraint as f
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Architecture Support Applicable Ele
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MAXDELAY (Maximum Delay) Architectu
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PCF Syntax item MAXDELAY = maxvalue
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MAXSKEW (Maximum Skew) The MAXSKEW
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FPGA Editor Syntax Chapter 4: Xilin
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MIODELAY_GROUP (MIODELAY Group) Arc
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UCF and NCF Syntax Chapter 4: Xilin
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where Chapter 4: Xilinx Constraints
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Falling Edge Constraints Chapter 4:
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PlanAhead Syntax Chapter 4: Xilinx
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where Chapter 4: Xilinx Constraints
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UCF Syntax NET “clock” TNM_NET
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Attribute OUT_TERM: string; Specify
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TIMESPEC PERIOD Method Chapter 4: X
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Examples of a Primary Clock with De
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where • period is the required cl
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New PERIOD Specifications Output Pi
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Post CRC (POST_CRC) Architecture Su
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Post CRC Frequency (POST_CRC_FREQ)
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Post CRC Signal (POST_CRC_SIGNAL) A
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PRIORITY (Priority) Architecture Su
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The following are not supported: Ch
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PULLDOWN (Pulldown) Architecture Su
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PULLUP (Pullup) Architecture Suppor
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PWR_MODE (Power Mode) Architecture
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REG (Registers) The REG (Registers)
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RLOC (Relative Location) The Relati
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RLOC = X3Y4 Chapter 4: Xilinx Const
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Linking Sets Set Linkage Chapter 4:
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Chapter 4: Xilinx Constraints by th
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Linking Two HU_SET Sets Chapter 4:
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Specify the VHDL constraint as foll
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Chapter 4: Xilinx Constraints Diffe
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H_SET (H Set) Chapter 4: Xilinx Con
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Chapter 4: Xilinx Constraints The n
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Syntax Examples Chapter 4: Xilinx C
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RLOC_RANGE (Relative Location Range
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where the relative X values (m1 and
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UCF and NCF Syntax NET “mysignal
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VHDL Syntax Chapter 4: Xilinx Const
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SLOW (Slow) The SLOW (Slow) constra
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STEPPING (Stepping) Architecture Su
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VHDL Syntax Chapter 4: Xilinx Const
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Chapter 4: Xilinx Constraints The f
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TIMEGRP (Timing Group) The TIMEGRP
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Defining Latch Subgroups by Gate Se
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Chapter 4: Xilinx Constraints When
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PCF Syntax TIMEGRP name; TIMEGRP na
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Separators FROM-TO Syntax TIMESPEC
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TNM (Timing Name) Chapter 4: Xilinx
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Chapter 4: Xilinx Constraints A qua
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TNM_NET (Timing Name Net) The TNM_N
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Schematic Syntax • Attach to a ne
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TPSYNC (Timing Point Synchronizatio
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UCF and NCF Syntax NET “net_name
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Using TPTHRU in a FROM TO Constrain
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TSidentifier (Timing Specification
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Ignoring Paths Note This form is no
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Chapter 4: Xilinx Constraints If yo
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Use Low Skew Lines (USELOWSKEWLINES
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VCCAUX (VCCAUX) Architecture Suppor
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VREF (VREF) The VREF (VREF) constra
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XBLKNM (XBLKNM) Architecture Suppor
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Additional Resources Appendix • X
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