Xilinx Constraints Guide

Post CRC (POST_CRC)
Architecture Support
Applicable Elements
Propagation Rules
Chapter 4: Xilinx Constraints
Post CRC (POST_CRC) enables or disables the configuration logic CRC error detection
feature allowing for notification of any possible change to the configuration memory.
For Spartan-3A devices, it also reserves the multi-use INIT pin for signaling of a
configuration CRC failure. This also allows the banking rules used by PlanAhead,
PAR, and BitGen to refrain from using the IOB that drives the INIT pin. During
configuration, the INIT pin operates as normal. After configuration, if POST_CRC
analysis is enabled, the INIT pin serves as a CRC status pin. If comparison of the
real-time computed CRC differs from the pre-computed CRC, a configuration memory
change has been detected and the INIT pin is driven low.
For more information, see the device data sheet.
Values for POST_CRC
Value Description
ENABLE Enables the Post CRC checking feature
DISABLE Disables the Post CRC checking features
(default)
Applies to Virtex®-5, Virtex-6, Spartan®-3A, and Spartan-6 devices.
Applies to the entire design.
Applies to the entire design.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
UCF Syntax
CONFIG POST_CRC = {ENABLE|DISABLE|ONESHOT};
PCF Syntax
CONFIG POST_CRC = {ENABLE|DISABLE|ONESHOT};
Constraints Guide
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