Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
Verilog Syntax
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* KEEPER = " {YES|NO|TRUE|FALSE}" *)
For more information about basic Verilog syntax, see Verilog Attributes.
UCF and NCF Syntax
This statement configures the IO to use KEEPER for a NET.
NET "pad_net_name" KEEPER;
This statement configures KEEPER to be used globally.
DEFAULT KEEPER = TRUE;
XCF Syntax
BEGIN MODEL “entity_name”
NET “signal_name” keeper={yes|no|true |false};
END;
Constraints Guide
156 www.xilinx.com UG625 (v. 13.2) July 6, 2011