Xilinx Constraints Guide

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Chapter 4: Xilinx Constraints Range Name virtex4 virtex5 virtex6 spartan6 BUFGMUX_XnYn X BUFHCE_XnYn X BUFH_XnYn X BUFIO2FB_XnYn X BUFIO2_XnYn X BUFIODQS_XnYn X BUFIO_XnYn X X BUFO_XnYn X BUFPLL_MCB_XnYn X BUFPLL_XnYn X BUFR_XnYn X X X CAPTURE_XnYn X CFG_IO_ACCESS_XnYn X CRC32_XnYn X CRC64_XnYn X DCIRESET_XnYn X DCI_XnYn X X X DCM_ADV_XnYn X X DCM_XnYn X DNA_PORT_XnYn X DPM_XnYn X DSP48_XnYn X X X X EFUSE_USR_XnYn X EMAC_XnYn X FIFO16_XnYn X GLOBALSIG_XnYn X X X GT11CLK_XnYn X GT11_XnYn X GTPA1_DUAL_XnYn X GTP_DUAL_XnYn X GTXE1_XnYn X GTX_DUAL_XnYn X IBUFDS_GTXE1_XnYn X ICAP_XnYn X X X X IDELAYCTRL_XnYn X X X ILOGIC_XnYn X X X X IOB_XnYn X X X IODELAY_XnYn X X X Constraints Guide 70 www.xilinx.com UG625 (v. 13.2) July 6, 2011
Chapter 4: Xilinx Constraints Range Name virtex4 virtex5 virtex6 spartan6 IPAD_XnYn X X X X MCB_XnYn X MMCM_ADV_XnYn X MONITOR_XnYn X OCT_CAL_XnYn X OLOGIC_XnYn X X X X OPAD_XnYn X X X X PCIE_XnYn X X X PCILOGIC_XnYn X PLL_ADV_XnYn X X PMCD_XnYn X PMVBRAM_XnYn X X PMVIOB_XnYn X PMV_XnYn X PPC405_ADV_XnYn X PPC440_XnYn X PPR_FRAME_XnYn X RAMB16_XnYn X X RAMB18_XnYn X RAMB36_XnYn X X RAMB8_XnYn X SLICE_XnYn X X X X STARTUP_XnYn X SYSMON_XnYn X X TEMAC_XnYn X X TIEOFF_XnYn X X X X USR_ACCESS_XnYn X Constraints Guide UG625 (v. 13.2) July 6, 2011 www.xilinx.com 71
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Constraints Guide UG625 (v. 13.2) J
Page 3 and 4:
Table of Contents Revision History
Page 5 and 6:
IBUF_DELAY_VALUE (Input Buffer Dela
Page 7 and 8:
Constraint Types Attributes and Con
Page 9 and 10:
Grouping Constraints for Timing Cha
Page 11 and 12:
The name qualifier can include the
Page 13 and 14:
Physical Constraints Mapping Note T
Page 15 and 16:
Placement Constraints Chapter 1: Co
Page 17 and 18:
Routing Directives Routing directiv
Page 19 and 20: Timing Constraints Chapter 1: Const
Page 21 and 22: UCF Timing Constraint Support From-
Page 23 and 24: Timing Model Constraint Priority Ch
Page 25 and 26: Chapter 2 Entry Strategies for Xili
Page 27 and 28: Constraint Schematic VHDL Verilog L
Page 29 and 30: An attribute can be declared in an
Page 31 and 32: User Constraints File (UCF) UCF Flo
Page 33 and 34: Syntax Chapter 2: Entry Strategies
Page 35 and 36: Entering Multiple Constraints File
Page 37 and 38: Chapter 2: Entry Strategies for Xil
Page 39 and 40: Running Constraints Editor As a Sta
Page 41 and 42: Defining I/O Pin Configurations Cha
Page 43 and 44: Placement LOC Constraint Assignment
Page 45 and 46: Verilog Example -------------module
Page 47 and 48: Chapter 2: Entry Strategies for Xil
Page 49 and 50: Timing Specification Priorities Cha
Page 51 and 52: Timing Constraint Strategies Chapte
Page 53 and 54: Chapter 3: Timing Constraint Strate
Page 55 and 56: The global OFFSET IN constraint for
Page 57 and 58: The PERIOD constraint syntax for th
Page 59 and 60: Example Chapter 3: Timing Constrain
Page 61 and 62: Chapter 3: Timing Constraint Strate
Page 63 and 64: The global OFFSET OUT constraints f
Page 65 and 66: Multi-Cycle Paths Chapter 3: Timing
Page 67 and 68: Xilinx Constraints Each Xilinx® co
Page 69: RANGE Chapter 4: Xilinx Constraints
Page 73 and 74: COMPRESSION GROUP PLACE Chapter 4:
Page 75 and 76: Defining From Timing Groups Chapter
Page 77 and 78: BEL (BEL) The BEL (BEL) constraint:
Page 79 and 80: BLKNM (Block Name) Architecture Sup
Page 81 and 82: BUFG (BUFG) The BUFG (BUFG) constra
Page 83 and 84: Clock Dedicated Route (CLOCK_DEDICA
Page 85 and 86: COMPGRP (Component Group) Architect
Page 87 and 88: • S_SELECTMAP16 Slave SelectMAP M
Page 89 and 90: Verilog Syntax Chapter 4: Xilinx Co
Page 93 and 94: PCF Syntax CONFIG DCI_CASCADE = ",
Page 95 and 96: Default (DEFAULT) Chapter 4: Xilinx
Page 97 and 98: Example (* KEEPER = “TRUE” *) D
Page 99 and 100: DIFF_TERM (Diff_Term) Architecture
Page 101 and 102: DIRECTED_ROUTING (Directed Routing)
Page 103 and 104: DISABLE (Disable) The DISABLE (Disa
Page 105 and 106: DRIVE (Drive) The DRIVE (Drive) con
Page 107 and 108: XCF Syntax MODEL “entity_name”
Page 109 and 110: ENABLE (Enable) The ENABLE (Enable)
Page 111 and 112: ENABLE_SUSPEND (Enable Suspend) Arc
Page 115 and 116: Constraints Editor Syntax Chapter 4
Page 117 and 118: VHDL Syntax Declare the VHDL constr
Page 119 and 120: UCF and NCF Syntax NET “signal_na
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Chapter 4: Xilinx Constraints You a
Page 123 and 124:
Constraints Editor Syntax Chapter 4
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HBLKNM (Hierarchical Block Name) Ar
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HIODELAY_GROUP (HIODELAY Group) Arc
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VHDL Syntax Declare the VHDL constr
Page 131 and 132:
HU_SET (HU Set) The HU_SET (HU Set)
Page 133 and 134:
IBUF_DELAY_VALUE (Input Buffer Dela
Page 135 and 136:
IFD_DELAY_VALUE (IFD Delay Value) T
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IN_TERM (In Term) Architecture Supp
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INREG (Input Registers) Architectur
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IOB (IOB) The IOB constraint: • I
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IOBDELAY (Input Output Block Delay)
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IODELAY_GROUP (IODELAY Group) Limit
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IOSTANDARD (Input Output Standard)
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Pinout and Area Constraints Editor
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Verilog Syntax Chapter 4: Xilinx Co
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Architecture Support Applicable Ele
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Keeper (KEEPER) Architecture Suppor
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LOC (Location) The LOC (Location) c
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Chapter 4: Xilinx Constraints The w
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LOC Range Constraint Examples Const
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PlanAhead Syntax Chapter 4: Xilinx
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Schematic LOC=P17 Chapter 4: Xilinx
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Example One Chapter 4: Xilinx Const
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Slices Prohibited Example Two Chapt
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LOCK_PINS (Lock Pins) Architecture
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where value is any chosen name unde
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MAP (Map) Architecture Support Appl
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Specify the Verilog constraint as f
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Architecture Support Applicable Ele
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MAXDELAY (Maximum Delay) Architectu
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PCF Syntax item MAXDELAY = maxvalue
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MAXSKEW (Maximum Skew) The MAXSKEW
Page 187 and 188:
FPGA Editor Syntax Chapter 4: Xilin
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MIODELAY_GROUP (MIODELAY Group) Arc
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Page 193 and 194:
UCF and NCF Syntax Chapter 4: Xilin
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where Chapter 4: Xilinx Constraints
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Falling Edge Constraints Chapter 4:
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PlanAhead Syntax Chapter 4: Xilinx
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where Chapter 4: Xilinx Constraints
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UCF Syntax NET “clock” TNM_NET
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Attribute OUT_TERM: string; Specify
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TIMESPEC PERIOD Method Chapter 4: X
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Examples of a Primary Clock with De
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where • period is the required cl
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New PERIOD Specifications Output Pi
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Post CRC (POST_CRC) Architecture Su
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Post CRC Frequency (POST_CRC_FREQ)
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Post CRC Signal (POST_CRC_SIGNAL) A
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PRIORITY (Priority) Architecture Su
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The following are not supported: Ch
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PULLDOWN (Pulldown) Architecture Su
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PULLUP (Pullup) Architecture Suppor
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PWR_MODE (Power Mode) Architecture
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REG (Registers) The REG (Registers)
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RLOC (Relative Location) The Relati
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RLOC = X3Y4 Chapter 4: Xilinx Const
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Linking Sets Set Linkage Chapter 4:
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Chapter 4: Xilinx Constraints by th
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Linking Two HU_SET Sets Chapter 4:
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Specify the VHDL constraint as foll
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Chapter 4: Xilinx Constraints Diffe
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H_SET (H Set) Chapter 4: Xilinx Con
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Chapter 4: Xilinx Constraints The n
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Syntax Examples Chapter 4: Xilinx C
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RLOC_RANGE (Relative Location Range
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where the relative X values (m1 and
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Page 261 and 262:
UCF and NCF Syntax NET “mysignal
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VHDL Syntax Chapter 4: Xilinx Const
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SLOW (Slow) The SLOW (Slow) constra
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STEPPING (Stepping) Architecture Su
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VHDL Syntax Chapter 4: Xilinx Const
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Page 275 and 276:
Constraints Editor Syntax Chapter 4
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Chapter 4: Xilinx Constraints The f
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TIMEGRP (Timing Group) The TIMEGRP
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Defining Latch Subgroups by Gate Se
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Chapter 4: Xilinx Constraints When
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PCF Syntax TIMEGRP name; TIMEGRP na
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Separators FROM-TO Syntax TIMESPEC
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TNM (Timing Name) Chapter 4: Xilinx
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Chapter 4: Xilinx Constraints A qua
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TNM_NET (Timing Name Net) The TNM_N
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Schematic Syntax • Attach to a ne
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TPSYNC (Timing Point Synchronizatio
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UCF and NCF Syntax NET “net_name
Page 301 and 302:
Using TPTHRU in a FROM TO Constrain
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TSidentifier (Timing Specification
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Ignoring Paths Note This form is no
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Page 309 and 310:
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Page 313 and 314:
Chapter 4: Xilinx Constraints If yo
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Use Low Skew Lines (USELOWSKEWLINES
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VCCAUX (VCCAUX) Architecture Suppor
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VREF (VREF) The VREF (VREF) constra
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XBLKNM (XBLKNM) Architecture Suppor
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Additional Resources Appendix • X
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