Xilinx Constraints Guide

Chapter 3: Timing Constraint Strategies
Register-to-Register Timing Constraints
This section discusses the methodology for the specification of register-to-register
synchronous path timing requirements. Register-to-register constraints cover the
synchronous data paths between internal registers. This section includes:
• Register-to-Register Timing Constraints Overview
• Automatically Related DCM/PLL/MMCM Clocks
• Manually Related Clock Domains
• Asynchronous Clock Domains
Register-to-Register Timing Constraints Overview
PERIOD defines the timing of the clock domains. PERIOD not only analyzes the paths
within a single clock domain, but analyzes all paths between related clock domains as
well. In addition, PERIOD automatically takes into account all frequency, phase, and
uncertainty differences between the domains during analysis.
The application and methodology for constraining synchronous clock domains falls
under several common categories. These categories include:
• Automatically related DCM/PLL/MMCM Clock Domains
• Manually related Clock Domains
• Asynchronous Clock Domains
By allowing the tools to automatically create clock relationships for DCM/PLL/MMCM
output clocks, and manually defining relationships for externally related clocks, all
synchronous cross-clock- domain paths will be covered by the appropriate constraints,
and properly analyzed. With proper application of PERIOD constraints that follows this
methodology, the need for additional cross-clock-domain constraints is eliminated.
Automatically Related DCM/PLL/MMCM Clocks
The most common type of clock circuit is one in which the input clock is fed into
a DCM/PLL/MMCM and the outputs are used to clock the synchronous paths in
the device. In this scenario, the recommended methodology is to define a PERIOD
constraint on the input clock to the DCM/PLL/MMCM . By placing PERIOD on the
input clock, the Xilinx® software automatically derives a new PERIOD for each of the
DCM/PLL/MMCM output clocks. In addition, the tools will automatically determine the
clock relationships between the output clock domains, and automatically perform an
analysis for any paths between these synchronous domains.
Example
In this example, the input clock goes to a DCM. The following figure shows the circuit
for this example:
Constraints Guide
56 www.xilinx.com UG625 (v. 13.2) July 6, 2011