Xilinx Constraints Guide

Chapter 3: Timing Constraint Strategies
Because this interface uses a common system clock, only the data will be transmitted
from the FPGA device to the receiving device.
Using OFFSET OUT is the most efficient way to specify the output timing for the system
synchronous interface. In the global method, one OFFSET OUT constraint is defined for
each system synchronous output interface clock. This single constraint covers the paths
of all output data bits sent from registers triggered by the specified output clock.
To specify the output timing:
1. Define a time name (TNM) for the output clock to create a timegroup which contains
all output registers triggered by the output clock.
2. Define the global the OFFSET OUT constraint for the interface
Example
The following example shows the interface and a timing diagram for a System
Synchronous SDR output interface. The data in this example must become valid at the
output pins a maximum of 5 ns after the input clock edge at the pin of the FPGA.
The global OFFSET OUT constraint for the system synchronous interface is defined as:
OFFSET = OUTvalue VALID value AFTER clock;
Constraints Guide
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