Xilinx Constraints Guide

VHDL Syntax
Declare the VHDL constraint as follows:
attribute S: string;
Specify the VHDL constraint as follows:
attribute S of signal_name : signal is ”{YES|NO|TRUE|FALSE }”;
For more information about basic VHDL syntax, see VHDL Attributes.
Verilog Syntax
Chapter 4: Xilinx Constraints
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* S = {YES|NO|TRUE|FALSE} *)
For more information about basic Verilog syntax, see Verilog Attributes.
UCF and NCF Syntax
The following statement specifies that the net or signal named $SIG_9 should not be
removed.
NET $SIG_9 S;
XCF Syntax
BEGIN MODEL entity_name
NET "signal_name" s=true;
END;
Constraints Guide
UG625 (v. 13.2) July 6, 2011 www.xilinx.com 259