Xilinx Constraints Guide

Post CRC Frequency (POST_CRC_FREQ)
The Post CRC Frequency (POST_CRC_FREQ) constraint:
• Is supported for the following devices only:
– Spartan®-3A
– Spartan-6
– Virtex®-6
• Is a configuration logic CRC error detection mode.
Chapter 4: Xilinx Constraints
A pre-computed CRC for the configuration bitstream is compared against a CRC
computed by internal logic based on periodic readback of the configuration memory
cells.
• Controls the frequency with which the configuration CRC check is performed for
all devices that support this constraint.
• Is applicable only when POST_CRC is set to ENABLE.
Frequency Range (MHz) Steps (MHz) Default Value (MHz)
Spartan-3A 1 to 100 1, 3, 6, 7, 8, 10, 12, 13, 17, 22,
25, 27, 33, 44, 50, 100
Spartan-6 1 to 100 1, 2, 4, 6, 10, 12, 16, 22, 26, 33,
40, 50, 66
Virtex-6 1 to 50 1, 2, 3, 6, 13, 25, 50 1
Architecture Support
Applicable Elements
Propagation Rules
Applies to Spartan®-3A, Spartan-6, and Virtex®-6 devices only.
Applies to the entire device and is not specified on any particular design element.
Applies to the entire design.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
UCF Syntax
CONFIG POST_CRC_FREQ = [1|3|6|7|8|10|12|13|17|22|25|27|33|44|50|100];
PCF Syntax
CONFIG POST_CRC_FREQ = [1|3|6|7|8|10|12|13|17|22|25|27|33|44|50|100];
Constraints Guide
UG625 (v. 13.2) July 6, 2011 www.xilinx.com 219
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