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Xilinx Constraints Guide

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The PERIOD constraint syntax for this example is:<br />

NET “ClockName” TNM_NET = “TNM_NET_Name”;<br />

Chapter 3: Timing Constraint Strategies<br />

TIMESPEC “TS_name” = PERIOD “TNM_NET_Name” PeriodValue HIGH HighValue%;<br />

For PERIOD, the PeriodValue defines the duration of the clock period. In this case, the<br />

input clock to the DCM has a period of 5 ns. The HighValue of the PERIOD constraint<br />

defines the percent of the clock waveform that is HIGH. In this example, the waveform<br />

has a 50/50 duty cycle resulting in a HighValue of 50%. The syntax for this example is:<br />

NET “ClkIn” TNM_NET = “ClkIn”;<br />

TIMESPEC “TS_ClkIn” = PERIOD “ClkIn” 5 ns HIGH 50%;<br />

Based on the input clock PERIOD constraint given above, the DCM automatically<br />

creates two output clock constraints for the DCM outputs, and automatically performs<br />

analysis between the two domains.<br />

Manually Related Clock Domains<br />

In some cases, the relationship between synchronous clock domains cannot be<br />

automatically determined by the tools. One example occurs when related clocks enter<br />

the FPGA device on separate pins. In this scenario, the recommended constraint<br />

methodology is to create separate PERIOD constraints for both input clocks and define<br />

a manual relationship between the clocks. Once the manual relationship is defined,<br />

all paths between the two synchronous domains are automatically analyzed with all<br />

frequency, phase, and uncertainty information automatically taken into account.<br />

The <strong>Xilinx</strong> constraints system allows for complex manual relationships to be defined<br />

between clock domains using PERIOD. This manual relationship can include clock<br />

frequency and phase transformations. The methodology for this process is:<br />

1. Define PERIOD for the primary clock<br />

2. Define the PERIOD constraint for the related clock using the first PERIOD constraint<br />

as a reference<br />

Example<br />

In this example two related clocks enter the FPGA device through separate external<br />

pins. The first clock, CLK1X, is the primary clock, and the second clock, CLK2X180 is<br />

the related clock. The circuit for this example is shown in the following figure:<br />

The PERIOD syntax for this example is:<br />

NET “PrimaryClock” TNM_NET = “TNM_Primary”;<br />

NET “RelatedClock” TNM_NET = “TNM_Related”;<br />

TIMESPEC “TS_primary” = PERIOD “TNM_Primary” PeriodValue HIGH HighValue%;<br />

TIMESPEC “TS_related” = PERIOD “TNM_Related” TS_Primary_relation PHASE value;<br />

<strong>Constraints</strong> <strong>Guide</strong><br />

UG625 (v. 13.2) July 6, 2011 www.xilinx.com 57

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