Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
VHDL Syntax
Declare the VHDL constraint as follows:
Attribute IN_TERM: string;
Specify the VHDL constraint as follows:
attribute IN_TERM of signal_name: signal is “{NONE | TUNED_SPLIT |
UNTUNED_SPLIT_25 | UNTUNED_SPLIT_50 | UNTUNED_SPLIT_75}”;
For more information about basic VHDL syntax, see VHDL Attributes.
Verilog Syntax
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* IN_TERM = “{NONE | TUNED_SPLIT | UNTUNED_SPLIT_25 |
UNTUNED_SPLIT_50 | UNTUNED_SPLIT_75 }” *)
For more information about basic Verilog syntax, see Verilog Attributes.
UCF and NCF Syntax
The following statement configures the IO to use a PULLUP.
NET "pad_net_name"IN_TERM = “{NONE | TUNED_SPLIT | UNTUNED_SPLIT_25
| UNTUNED_SPLIT_50 | UNTUNED_SPLIT_75 }” ;
The following statement configures IN_TERM to be used globally.
DEFAULT IN_TERM = TUNED_SPLIT;
XCF Syntax
BEGIN MODEL “entity_name”
NET "signal_name" in_term=tuned_split;
END;
PlanAhead Syntax
For more information about using the PlanAhead software to create constraints, see
Floorplanning the Design in the PlanAhead User Guide (UG632). See PlanAhead in this
Guide for information about:
• Defining placement constraints
• Assigning placement constraints
• Defining I/O pin configurations
• Floorplanning and placement constraints
Constraints Guide
138 www.xilinx.com UG625 (v. 13.2) July 6, 2011