Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
The wildcard character for an FPGA global buffer, global pad, or DCM locations, is
not supported.
LOC Description for CPLD Devices
LOC Priority
Architecture Support
Applicable Elements
Propagation Rules
Constraint Syntax
For CPLD devices, use the LOC=pin_name constraint on a PAD symbol or pad net to
assign the signal to a specific pin. The PAD symbols are IPAD, OPAD, IOPAD, and
UPAD. You can use the LOC=FBnn constraint on any instance or its output net to assign
the logic or register to a specific function block or macrocell, provided the instance is
not collapsed.
The LOC=FB nn_mm constraint on any internal instance or output pad assigns the
corresponding logic to a specific function block or macrocell within the CPLD. If a LOC
is placed on a symbol that does not get mapped to a macrocell or is otherwise removed
through optimization, the LOC is ignored.
When specifying two adjacent LOC constraints on an input pad and its adjoining net,
the LOC attached to the net has priority. In the following diagram, LOC=11 takes
priority over LOC=38.
LOC Priority Example
Applies to all FPGA devices and all CPLD devices.
For information about which design elements can be used with which device families,
see the Libraries Guides. For more information, see the device data sheet.
For all nets, LOC is illegal when attached to a net or signal except when the net or signal
is connected to a pad. In this case, LOC is treated as attached to the pad instance.
For CPLD nets, LOC attaches to all applicable elements that drive the net or signal.
When attached to a design element, LOC propagates to all applicable elements in the
hierarchy within the design element.
Following is the syntax for a single location:
INST “instance_name” LOC=location;
where
location is a legal location for the part type
Constraints Guide
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