Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
COLLAPSE (Collapse)
Architecture Support
Applicable Elements
The COLLAPSE (Collapse) constraint:
• Is an advanced fitter constraint.
• Forces a combinatorial node to be collapsed into all of its fanouts.
Applies to CPLD devices only. Does not apply to FPGA devices.
Any internal net.
Propagation Rules
This constraint is a net constraint. Any attachment to a design element is illegal.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Schematic Syntax
• Attach to a logic symbol or its output net
• Attribute Name
COLLAPSE
• Attribute Values
– TRUE
– FALSE
VHDL Syntax
Declare the VHDL constraint as follows:
attribute collapse: string;
Specify the VHDL constraint as follows:
attribute collapse of signal_name: signal is “{YES|NO|TRUE|FALSE}”;
For more information about basic VHDL syntax, see VHDL Attributes.
Verilog Syntax
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* COLLAPSE = “{YES|NO|TRUE|FALSE}” *)
For more information about basic Verilog syntax, see Verilog Attributes.
UCF and NCF Syntax
NET “net_name” COLLAPSE;
The following statement forces net $1N6745 to collapse into all its fanouts.
NET “$1I87/$1N6745” COLLAPSE;
Constraints Guide
84 www.xilinx.com UG625 (v. 13.2) July 6, 2011