Xilinx Constraints Guide

where
value
is any chosen name under which you want to group the two elements.
Example
Chapter 4: Xilinx Constraints
architecture MY_DESIGN of top is
attribute LUTNM: string;
attribute LUTNM of LUT5_inst1: label is "logic_group1";
attribute LUTNM of LUT5_inst2: label is "logic_group1";
begin
-- LUT5: 5-input Look-Up Table
-- Virtex-5
-- Xilinx HDL Libraries Guide version 8.2i
LUT5_inst1 : LUT5
generic map (
INIT => X"a49b44c1")
port map (
O => aout, -- LUT output (1-bit)
I0 => d(0), -- LUT input (1-bit)
I1 => d(1), -- LUT input (1-bit)
I2 => d(2), -- LUT input (1-bit)
I3 => d(3), -- LUT input (1-bit)
I4 => d(4) -- LUT input (1-bit)
);
-- End of LUT5_inst1 instantiation
-- LUT5: 5-input Look-Up Table
-- Virtex-5
-- Xilinx HDL Libraries Guide version 8.2i
LUT5_inst2 : LUT5
generic map (
INIT => X"649d610a")
port map (
O => bout, -- LUT output (1-bit)
I0 => d(0), -- LUT input (1-bit)
I1 => d(1), -- LUT input (1-bit)
I2 => d(2), -- LUT input (1-bit)
I3 => d(3), -- LUT input (1-bit)
I4 => d(4) -- LUT input (1-bit)
);
-- End of LUT5_inst2 instantiation
END MY_DESIGN;
For more information about basic VHDL syntax, see VHDL Attributes.
Verilog Syntax
Place the following attribute specification before the port declaration in the top-level
Verilog code:
(* LUTNM = "value" *)
where
value is any chosen name under which you want to group the two elements.
Constraints Guide
UG625 (v. 13.2) July 6, 2011 www.xilinx.com 173