Xilinx Constraints Guide

Timing Constraints
Chapter 1: Constraint Types
The Xilinx® software enables you to specify precise timing requirements using either
global or path-specific timing constraints.
The recommended methods for defining the constraints are discussed in Timing
Constraint Strategies.
Timing and Grouping Constraints
The following are timing constraints and associated grouping constraints:
• Asynchronous Register (ASYNC_REG)
• Disable (DISABLE)
• Drop Specifications (DROP_SPEC)
• Enable (ENABLE)
• From Thru To (FROM-THRU-TO)
• From To (FROM-TO)
• Maximum Skew (MAXSKEW)
• Offset In (OFFSET IN)
• Offset Out (OFFSET OUT)
• Period (PERIOD)
• Priority (PRIORITY)
• System Jitter (SYSTEM_JITTER)
• Temperature (TEMPERATURE)
• Timing Ignore (TIG)
• Timing Group (TIMEGRP)
• Timing Specifications (TIMESPEC)
• Timing Name (TNM)
• Timing Name Net (TNM_NET)
• Timing Point Synchronization (TPSYNC)
• Timing Thru Points (TPTHRU)
• Timing Specification Identifier (TSidentifier)
• Voltage (VOLTAGE)
Specifying Timing Constraints
To specify timing constraints, enter them in:
• User Constraints File (UCF) (primary method), or
• HDL source code, or
• Schematic source code.
Once you have defined the timing specifications and mapped the design, PAR places
and routes the design based on these specifications.
To analyze the results of the timing specifications, use:
• Timing Analyzer (ISE® Design Suite), or
• TRACE (command line).
Constraints Guide
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