Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
The following constraint would be attached to a net to inform the timing analysis tools
that it should ignore paths through the net for specification TS43.
Schematic Syntax TIG = TS43
UCF Syntax NET “ net_name” TIG = TS43;
You cannot perform path analysis in the presence of combinatorial loops. Therefore,
the timing software ignores certain connections to break combinatorial loops. You can
use the TIG constraint to direct the timing tools to ignore specified nets or load pins,
consequently controlling how loops are broken.
Syntax
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Note TIG does not affect the timing reported at the bottom of the XST report. TIG
applies only to the timing reported by Timing Analyzer.
Schematic Syntax
• Attach to a net or pin
• Attribute Name
TIG
• Attribute Values
value
UCF and NCF Syntax
NET “ net_name” TIG;
PIN “ff_inst.RST” TIG=TS_1;
INST “instance_name ” TIG=TS_2;
TIG=TS identifier1 . . . TS identifiern
identifier refers to a timing specification that should be ignored
When attached to an instance, TIG is pushed to the output pins of that instance. When
attached to a net, TIG pushes to the drive pin of the net. When attached to a pin, TIG
applies to the pin.
The following statement specifies that the timing specifications TS_fast and
TS_even_faster is ignored on all paths fanning forward from the net RESET.
NET “RESET” TIG=TS_fast, TS_even_faster;
XST Constraint File (XCF) Syntax
The XST Constraint File (XCF) syntax is the same as the User Constraints File (UCF)
syntax.
XST fully supports the TIG constraint. TIG can be applied to the nets, situated in the
CORE files:
• Electronic Data Interchange Format (EDIF)
• Native Generic Database (NGD)
Constraints Editor Syntax
For information on Constraints Editor and Constraints Editor syntax in ISE® Design
Suite, see the ISE Design Suite Help.
Constraints Guide
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