Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
ASYNC_REG (Asynchronous Register)
The ASYNC_REG (Asynchronous Register) constraint:
• Is a timing constraint.
Architecture Support
Applicable Elements
Propagation Rules
Syntax Examples
• Is used to improve the behavior of asynchronously clocked data for simulation.
• Disables X propagation during timing simulation. In the event of a timing violation,
the previous value is retained on the output instead of going unknown.
Applies to FPGA devices. Does not apply to CPLD devices.
• Can be attached to registers and latches only.
• Should be used only on registers or latches with asynchronous inputs (D input
or the CE input).
Applies to the register or latch to which it is attached.
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
VHDL Syntax
Declare the VHDL constraint as follows:
attribute ASYNC_REG : string;
Specify the VHDL constraint as follows:
attribute ASYNC_REG of instance_name: label is "{TRUE|FALSE}";
For more information about basic VHDL syntax, see VHDL Attributes.
Verilog Syntax
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* ASYNC_REG = " {TRUE|FALSE}" *)
For more information about basic Verilog syntax, see Verilog Attributes.
UCF and NCF Syntax
INST “instance_name ” ASYNC_REG = {TRUE|FALSE};
The default is FALSE.
If no Boolean value is supplied, it is considered TRUE.
Constraints Editor Syntax
For information on setting constraints in Constraints Editor, including syntax, see the
Constraints Editor Help.
Constraints Guide
76 www.xilinx.com UG625 (v. 13.2) July 6, 2011