Xilinx Constraints Guide

UCF Syntax
NET “clock” TNM_NET = CLK;
TIMESPEC TS_CLK = PERIOD CLK 5.0 ns HIGH 50%;
Chapter 4: Xilinx Constraints
OFFSET = OUT AFTER clock REFERENCE_PIN “TxClock” RISING;
OFFSET = OUT AFTER clock REFERENCE_PIN “TxClock” FALLING;
UCF System Synchronous SDR Example
The System Synchronous Single Data Rate (SDR) case consists of an interface where the
input clock is used to transmit the data to the receiving device. In the SDR interface,
data is transmitted once per clock cycle. In this case a single OFFSET OUT requirement
is needed to constrain the interface.
In this example a clock signal called clock enters the FPGA. This clock signal trigger
the data output synchronous elements. Because this is a system synchronous interface,
the absolute clock to output time is required to constraint the interface. In this case,
a regenerated clock is not present, and the REFERENCE_PIN keyword is omitted to
request the default skew reporting.
UCF Syntax
NET “clock” TNM_NET = CLK;
TIMESPEC TS_CLK = PERIOD CLK 5.0 ns HIGH 50%;
OFFSET = OUT 5 ns AFTER “clock”;
Schematic Syntax
• Attach to a specific net
• Attribute Name: OFFSET
• Attribute Values: OUT offset_time BEFORE|AFTER clk_pad_netname
XCF Syntax
The XCF syntax is the same as the UCF syntax. However, the XCF syntax supports
only the OFFSET OUT AFTER method.
Constraints Editor Syntax
For information on Constraints Editor and Constraints Editor syntax in ISE® Design
Suite, see the ISE Design Suite Help.
PlanAhead Syntax
For more information about using the PlanAhead software to create constraints, see
Floorplanning the Design in the PlanAhead User Guide (UG632). See PlanAhead in this
Guide for information about:
• Defining placement constraints
• Assigning placement constraints
• Defining I/O pin configurations
• Floorplanning and placement constraints
Constraints Guide
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