Xilinx Constraints Guide

PULLDOWN (Pulldown)
Architecture Support
Applicable Elements
The PULLDOWN (Pulldown) constraint:
• Is a basic mapping constraint.
Chapter 4: Xilinx Constraints
• Guarantees a logic Low level to allow tri-stated nets to avoid floating when not
being driven.
KEEPER, PULLUP, and PULLDOWN are valid only on pad NETs, not on INSTs of
any kind.
Applies to all FPGA devices and the CoolRunner-II CPLD device only.
• Input
• Tristate outputs
Propagation Rules
• Bidirectional pad nets
This constraint is a net constraint. Any attachment to a design element is illegal.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Schematic Syntax
• Attach to a pad net
• Attribute Name
PULLDOWN
• Attribute Values
TRUE
FALSE
VHDL Syntax
Declare the VHDL constraint as follows:
attribute PULLDOWN: string;
Specify the VHDL constraint as follows:
attribute PULLDOWN of signal_name: signal is “{YES|NO|TRUE|FALSE}”;
For more information about basic VHDL syntax, see VHDL Attributes.
Verilog Syntax
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* PULLDOWN = “{YES|NO|TRUE|FALSE}” *)
For more information about basic Verilog syntax, see Verilog Attributes.
Constraints Guide
UG625 (v. 13.2) July 6, 2011 www.xilinx.com 227