Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
attribute XBLKNM: string;
Specify the VHDL constraint as follows:
attribute XBLKNM of {component_name|label_name}: {component|label} is block_name;
For more information about basic VHDL syntax, see VHDL Attributes.
Verilog Syntax
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* XBLKNM = "block_name" *)
For more information about basic Verilog syntax, see Verilog Attributes.
UCF and NCF Syntax
INST "instance_name" XBLKNM=block_name;
The following statement assigns an instantiation of an element named flip_flop2 to a
block named U1358.
INST "$1I87/flip_flop2" XBLKNM=U1358;
XCF Syntax
BEGIN MODEL "entity_name"
INST "instance_name" xblknm=xblknm_name;
END;
Constraints Guide
324 www.xilinx.com UG625 (v. 13.2) July 6, 2011