Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
Syntax
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Schematic Syntax
• Attach to a valid instance
• Attribute Name
HBLKNM
• Attribute Values
block_name
VHDL Syntax
Declare the VHDL constraint as follows:
attribute hblknm: string;
Specify the VHDL constraint as follows:
attribute hblknm of {entity_name|component_name|signal_name|label_name}:
{entity|component|signal|label} is “block_name”;
where
block_name is a valid block name for that type of symbol
For more information about basic VHDL syntax, see VHDL Attributes.
Verilog Syntax
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* HBLKNM = “block_name” *)
block_name is a valid block name for that type of symbol
For more information about basic Verilog syntax, see Verilog Attributes.
UCF and NCF Syntax
NET “net_name” HBLKNM=property_value;
INST “instance_name” HBLKNM=block_name;
block_name is a valid block name for that type of symbol
The following statement specifies that the element this_fmap is put into the block named
group1.
INST “$I13245/this_fmap” HBLKNM=group1;
The following statement attaches HBLKNM to the pad connected to net1.
NET “net1” HBLKNM=$COMP_0;
Elements with the same HBLKNM are placed in the same logic block if possible.
Otherwise an error occurs. Conversely, elements with different block names are not
put into the same block.
Constraints Guide
126 www.xilinx.com UG625 (v. 13.2) July 6, 2011