Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
VHDL Syntax
Declare the VHDL constraint as follows:
attribute USE_RLOC: string;
Specify the VHDL constraint as follows:
attribute USE_RLOC of entity_name: entity is “{TRUE | FALSE}”;
For more information about basic VHDL syntax, see VHDL Attributes.
Verilog Syntax
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* USE_RLOC = “{TRUE|FALSE}” *)
For more information about basic Verilog syntax, see Verilog Attributes.
UCF and NCF Syntax
INST “instance_name” USE_RLOC={TRUE | FALSE};
XCF Syntax
MODEL “entity_name” use_rloc={true | false};
Constraints Guide
314 www.xilinx.com UG625 (v. 13.2) July 6, 2011