Xilinx Constraints Guide

Architecture Support
Applicable Elements
Propagation Rules
Applies to all FPGA devices. Does not apply to CPLD devices.
Chapter 4: Xilinx Constraints
When the value is an integer, Max Fanout applies globally, or to a VHDL entity, a Verilog
module, or signal.
When the value is REDUCE, Max Fanout applies only to a signal.
Applies to the entity, module, or signal to which it is attached.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
VHDL Syntax
Declare the VHDL constraint as follows:
attribute max_fanout: string;
Specify the VHDL constraint as follows:
attribute max_fanout of {signal_name|entity_name}: {signal|entity} is "integer";
For more information about basic VHDL syntax, see VHDL Attributes.
Verilog Syntax
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* max_fanout = "integer" *)
XCF Syntax Example One
MODEL "entity_name" max_fanout=integer;
XCF Syntax Example Two
BEGIN MODEL "entity_name"
NET "signal_name" max_fanout=integer;
END;
XST Command Line Syntax
Define globally with the -max_fanout command line option of the run command:
-max_fanout integer
ISE Design Suite Syntax
Define globally in ISE Design Suite in Process > Properties > Xilinx-Specific Options >
Max Fanout.
Constraints Guide
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