Xilinx Constraints Guide

HBLKNM (Hierarchical Block Name)
Architecture Support
Applicable Elements
The HBLKNM (Hierarchical Block Name) constraint:
• Is an advanced mapping constraint.
Chapter 4: Xilinx Constraints
• Assigns hierarchical block names to logic elements and controls grouping in a
flattened hierarchical design. When elements on different levels of a hierarchical
design carry the same block name, and the design is flattened, NGCBuild prefixes a
hierarchical path name to the HBLKNM value.
Like Block Name, HBLKNM forces function generators and flip-flops into the same CLB.
Symbols with the same HBLKNM constraint map into the same CLB, if possible.
However, using HBLKNM instead of Block Name has the advantage of adding hierarchy
path names during translation, and therefore the same HBLKNM constraint and value
can be used on elements within different instances of the same design element.
Applies to FPGA devices. Does not apply to CPLD devices.
HBLKNM may be used with an FPGA device in one or more of the following design
elements, or categories of design elements. Not all devices support all elements. To see
which design elements can be used with which device families, see the Xilinx® Libraries
Guides for details. For more information, see the device data sheet.
• Registers
• I/O elements and pads
• FMAP
• PULLUP
• ACLK
• GCLK
• BUFG
• BUFGS
• BUFGP
• ROM
• RAMS
• RAMD
Propagation Rules
• Carry logic primitives
You can also attach HBLKNM to the net connected to the pad component in a UCF file.
NGCBuild transfers the constraint from the net to the pad instance in the NGD file so
that it can be processed by the mapper. Use the following syntax:
NET “net_name” HBLKNM=property_value;
When attached to a design element, HBLKNM is propagated to all applicable elements
in the hierarchy within the design element. However, when attached to a NET,
HBLKNM is only propagated to PADs.
Constraints Guide
UG625 (v. 13.2) July 6, 2011 www.xilinx.com 125