Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
FEEDBACK (Feedback)
The FEEDBACK (Feedback) constraint:
• Is used to define the external DCM feedback path delay when the DCM is used in
board de-skew applications. The delay is defined as the maximum external path
delay of the board trace and should not include any internal FPGA path delays.
• Is required for the timing tools to properly determine the DCM phase shift and
analyze the associated synchronous paths.
• input_feedback_clock_net
The name of the input pad net used as the feedback to the DCM
• value
The board trace delay calculated or measured by you
• units
ns (default) or ps
• output_clock_net
Architecture Support
Applicable Elements
The name of the output pad net driven by the DCM
Applies to FPGA devices. Does not apply to CPLD devices.
Not applicable.
Propagation Rules
Both input_feedback_clock_net and output_clock_net must correspond to pad nets. If
attached to any other net, an error results. The input_feedback_clock_net must be an input
pad and output_clock_net must be an output pad.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
UCF Syntax
NET output_clock_net FEEDBACK = value
units NET input_feedback_clock_net ;
XCF Syntax
BEGIN MODEL “entity_name ”
NET output_clock_net FEEDBACK = value units NET input_feedback_clock_net;
END;
PCF Syntax
BEL |COMP} output_clock_net FEEDBACK = value units {BEL |COMP}
input_feedback_clock_net;
Constraints Guide
114 www.xilinx.com UG625 (v. 13.2) July 6, 2011