Xilinx Constraints Guide

VHDL Syntax
Declare the VHDL constraint as follows:
attribute hlutnm: string;
Specify the VHDL constraint as follows:
attribute hlutnm of instance_name : label is “string_value ”;
where
Chapter 4: Xilinx Constraints
• instance_name is the instance name of an instantiated LUT, or LUTRAM.
• string_value is applied uniquely to two symbols within a given level of hierarchy.
– There is no default value.
– If the value is blank, the constraint is ignored.
For more information about basic VHDL syntax, see VHDL Attributes.
Verilog Syntax
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* HLUTNM = “string_value” *)
where
• string_value is applied uniquely to two symbols within a given level of hierarchy.
• There is no default value.
• If the value is blank, the constraint is ignored.
For more information about basic Verilog syntax, see Verilog Attributes.
UCF and NCF Syntax
INST “symbol_name” HLUTNM=string_value ;
where
• string_value is applied uniquely to two symbols within a given level of hierarchy.
• There is no default value.
• If the value is blank, the constraint is ignored.
XCF Syntax
MODEL “symbol_name” hlutnm = string_value ;
where
• string_value is applied uniquely to two symbols within a given level of hierarchy.
• There is no default value.
• If the value is blank, the constraint is ignored.
Constraints Guide
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