Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
OUT_TERM (Out Term)
The OUT_TERM (Out Term) constraint:
• Is a basic mapping constraint.
• Sets a configuration of output termination resistors
Out Term is valid:
• on an output pad NET
• on an output pad INST
• for the entire design
Architecture Support
Applicable Elements
Applies to FPGA devices. Does not apply to CPLD devices.
This constraint may be used with an FPGA device in one or more of the following design
elements, or categories of design elements:
• IOB input components (such as IBUF)
• Output Pad Net
Propagation Rules
Not all devices support all elements. To see which design elements can be used with
which devices, see the Libraries Guides. For more information, see the device data sheet.
OUT_TERM is illegal when attached to a net or signal, except when the net or signal is
connected to a pad. In this case, OUT_TERM is treated as attached to the pad instance.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Values
• NONE
• TUNED
• UNTUNED_25
• UNTUNED_50
• UNTUNED_75
Schematic Syntax
• Attach to a pad net
• Attribute Name
OUT_TERM
• Attribute Values
See Values section above.
VHDL Syntax
Declare the VHDL constraint as follows:
Constraints Guide
206 www.xilinx.com UG625 (v. 13.2) July 6, 2011