Xilinx Constraints Guide

VHDL Syntax
Chapter 4: Xilinx Constraints
Before using this constraint, declare it with the following syntax placed after the
architecture declaration but before the begin statement in the top-level VHDL file:
attribute SUSPEND: string;
After the constraint has been declared, specify the VHDL constraint as follows:
attribute SUSPEND of {top_level_port_name} : signal is "value";
Example:
entity top is
port (STATUS: out std_logic);
end top;architecture MY_DESIGN of top is
attribute SUSPEND: string;
attribute SUSPEND of STATUS: signal is "DRIVE_LAST_VALUE";
begin
For more information about basic VHDL syntax, see VHDL Attributes.
Verilog Syntax
Place the following attribute specification before the port declaration in the top-level
Verilog code:
(* SUSPEND="value" *)
Example:
module top ( (* SUSPEND="DRIVE_LAST_VALUE" *) output STATUS );
For more information about basic Verilog syntax, see Verilog Attributes.
UCF and NCF Syntax
Placed on an output or bi-directional port:
NET "top_level_port_name" SUSPEND="value";
Example:
NET "STATUS" SUSPEND="DRIVE_LAST_VALUE";
PACE Syntax
To set this constraint from the Pinout and Area Constraints Editor (PACE), select the
appropriate pin value from the Design Objects window.
Constraints Guide
UG625 (v. 13.2) July 6, 2011 www.xilinx.com 271