Xilinx Constraints Guide

Chapter 2: Entry Strategies for Xilinx Constraints
Pin Assignment
To invoke I/O Planner standalone either click the PlanAhead Windows Desktop icon
or enter PlanAhead on the Linux command line. From ISE Design Suite, you can use
any of the following methods to start your pin assignment process, which allows you to
choose the method most convenient for you:
• Floorplanning I/O – Pre-Synthesis
When using this command or process step, the HDL source files are passed to the
PlanAhead software in order to extract the top level I/O port information only. If a
UCF files exists in the ISE Design Suite project, it is passed to the PlanAhead software
for modification. If a UCF does not exist, you are prompted to create one. If multiple
UCF files exist, you are prompted to select the desired file to add new constraints to.
Existing constraints are modified in whichever file they are contained in.
Refer to the I/O Planner Documentation section for information on using the I/O
Planner environment contained in the PlanAhead software.
Once the I/O pin assignment is made, you save the PlanAhead software project and
exit the PlanAhead software. This updates the UCF files in the ISE Design Suite
project and update the project status accordingly. Exiting the PlanAhead software
without saving does not change the ISE Design Suite UCF source files or status.
• Floorplanning a Design – Post-Synthesis
When using this command or process step, the synthesized netlist source files are
passed to the PlanAhead software. If a UCF files exists in the ISE Design Suite
project, it is passed to the PlanAhead software for modification. If a UCF does not
exist, you are prompted to create one. If multiple UCF files exist, you are prompted
to select the desired file to add new constraints to. Existing constraints are modified
in whichever file they are contained in.
Having a synthesized netlist as input enables more functionality in I/O Planner since
the tool is now aware of the clocks and clock related logic in the design. Additional
I/O planning capabilities and DRCs are provided to make more intelligent pin
assignment decisions. The design connectivity can also be analyzed to ensure
optimized use of device resources in relation to the I/Os.
Refer to the I/O Planner Documentation section for information on using the I/O
Planner environment contained in the PlanAhead software.
Once the I/O pin assignment is made, you will then save the PlanAhead software
project and exit the PlanAhead software. This will update the UCF files in the Project
Navigator project and update the project status accordingly. Exiting PlanAhead
without saving with not change the ISE Design Suite UCF source files or status.
I/O Planning Documentation
The PlanAhead User Guide (UG632) contains a section on I/O planning for analyzing the
device resources and I/O pin assignment.
The PlanAhead Software Tutorial: I/O Pin Planning (UG674), and the Pin Planning
Methodology Guide (UG792) are also available.
Floorplanning and Placement Constraints
The PlanAhead software provides a comprehensive environment for analyzing the
design from a number of different aspects including connectivity, density, and timing.
You can then apply placement constraints to help drive the implementation tools toward
better or more consistent results. These constraints may include LOC constraints to lock
specific logic objects into specific sites on the device or AREA_GROUP constraints to
constrain a group of logic within a specific area of the device.
Constraints Guide
42 www.xilinx.com UG625 (v. 13.2) July 6, 2011