Xilinx Constraints Guide

ENABLE (Enable)
The ENABLE (Enable) constraint:
• Is a timing constraint.
Architecture Support
Applicable Elements
Propagation Rules
• Turns on specific path tracing controls.
Chapter 4: Xilinx Constraints
A path tracing control is used to determine if a common type of paths is enabled or
disabled for timing analysis. For more information, see Disable (DISABLE).
Applies to FPGA devices. Does not apply to CPLD devices.
Global in constraints file
Enables timing analysis for specified path delays.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
UCF and NCF Syntax
ENABLE can be applied only to a global timespec. The UCF path tracing syntax is
as follows:
ENABLE= delay_symbol_name ;
Where delay_symbol_name is the name of one of the standard block delay symbols for
path tracing symbols shown in the following table, or a specific delay name defined in
the data sheet
Constraints Guide
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