Xilinx Constraints Guide

LOCK_PINS (Lock Pins)
Architecture Support
Applicable Elements
Propagation Rules
The LOCK_PINS (Lock Pins) constraint:
Chapter 4: Xilinx Constraints
• Instructs the implementation tools to not swap the pins of the LUT symbol to which
it is attached.
• Is distinct from the Lock Pins process in ISE® Design Suite, which is used to preserve
the existing pinout of a CPLD design.
Applies to FPGA devices. Does not apply to CPLD devices.
Applies only to specific instances of LUT symbols.
Applies only to a single LUT instance.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
VHDL Syntax
Declare the VHDL constraint as follows:
attribute lock_pins: string;
Specify the VHDL constraint as follows:
attribute lock_pins of {component_name|label_name} : {component|label} is “all”;
For more information about basic VHDL syntax, see VHDL Attributes.
Verilog Syntax
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* LOCK_PINS = “all” *)
For more information on basic Verilog syntax, see Verilog Attributes.
UCF and NCF Syntax
• Using No Designator
INST “XSYM1” LOCK_PINS;
• Using the ALL Attribute
INST “XSYM1” LOCK_PINS=’ALL’;
• Using a PIN Assignment List
INST I_589 LOCK_PINS=I0:A2;
INST I_894 LOCK_PINS=I3:A1,I2:A4;
INST tvAgy LOCK_PINS=I0:A4,I1:A3,I2:A2,I3:A1;
Constraints Guide
UG625 (v. 13.2) July 6, 2011 www.xilinx.com 171