Xilinx Constraints Guide

TNM_NET (Timing Name Net)
The TNM_NET (Timing Name Net) constraint:
• Is a basic grouping constraint.
Chapter 4: Xilinx Constraints
• Identifies the elements that make up a group, which can then be used in a timing
specification.
• Is essentially equivalent to Timing Name (TNM) on a net except for input pad nets
Special rules apply when using Timing Name (TNM) with Period (PERIOD) for
DLL, DCM, PLL, and MMCM. For more information, see PERIOD Specifications on
CLKDLLs, DCMs, PLLs, and MMCM.
A TNM_NET is a property normally used in conjunction with an HDL design to
tag a specific net. All downstream synchronous elements and pads tagged with the
TNM_NET identifier are considered a group.
TNM_NET tags specific synchronous elements, pads, and latches as members of a group
to simplify the application of timing specifications to the group. NGCBuild never
transfers a Timing Name (TNM) constraint from the attached net to an input pad, as it
does with Timing Name (TNM).
TNM and TNM_NET
Placing TNM on a net groups together flip-flops, latches, RAM, or pads driven by
that net.
TNM does not propagate through IBUF or BUFG components. The TNM will end up
on the input pad.
Alternatively, the TNM_NET attribute does propagate through IBUF and global clock
buffers.
Xilinx® recommends:
Architecture Support
Applicable Elements
Rules
• Use TNM to group instances and macros (hierarchical blocks)
• To group input pads, use a TNM on the net, driven by a pad.
• Use TNM_NET to group several (many) logic elements driven by a net, such as
clocks, clock enables, chip enables, read/writes, and resets.
Applies to FPGA devices. Does not apply to CPLD devices.
Nets
The following rules apply to TNM_NET:
• TNM_NET constraints applied to pad nets propagate forward through the IBUF or
OBUF and any other combinatorial logic to synchronous logic or pads.
• TNM_NET constraints applied to a clock-pad-net propagate forward through the
clock buffer.
• Special rules apply when using TNM_NET with Period (PERIOD) for Virtex®-4
and Virtex-5 DLLs, DCMs, and PLLs.
Use TNM_NET to define certain types of nets that cannot be adequately described
by the Timing Name (TNM) constraint.
Constraints Guide
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