Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
COOL_CLK (CoolCLOCK)
Architecture Support
Applicable Elements
Propagation Rules
COOL_CLK (CoolCLOCK) reduces clocking power within a CPLD device by combining
clock division circuitry with the DualEDGE circuitry. Because the clock net can be
a significant power drain, the clock power can be reduced by driving the net at half
frequency, then doubling the clock rate using DualEDGE triggered macrocells.
Applies to CoolRunner-II devices only.
Applies to any input pad or internal signal driving a register clock.
Applying COOL_CLK to a clock net is equivalent to passing the clock through a
divide-by-two clock divider (CLK_DIV2) and replacing all flip-flops controlled by that
clock with DualEDGE flip-flops. Using COOL_CLK does not alter your overall design
functionality.
Some restrictions apply:
• You cannot use COOL_CLK on a clock that triggers any flip-flop on the low-going
edge. The CoolRunner-II clock divider can be triggered only on the high-rising
edge of the clock signal.
• If there are any DualEDGE flip-flops in your design source, the clock that controls
any of them cannot be specified as a COOL_CLK.
• If there is already a clock divider in your design source, you cannot also use
COOL_CLK. CoolRunner-II devices contain only one clock divider.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Schematic Syntax
• Attach to a input pad or internal signal driving a register clock
• Attribute Name
COOL_CLK
• Attribute Values
– TRUE
– FALSE
VHDL Syntax
Declare the VHDL constraint as follows:
attribute cool_clk: string;
Specify the VHDL constraint as follows:
attribute cool_clk of signal_name: signal is “{TRUE | FALSE}”;
For more information about basic VHDL syntax, see VHDL Attributes.
Constraints Guide
88 www.xilinx.com UG625 (v. 13.2) July 6, 2011