Xilinx Constraints Guide

Chapter 2: Entry Strategies for Xilinx Constraints
Verilog Limitations
Verilog Attributes Syntax Example Four
(* mult_style = "pipe_lut" *) MULT my_mult (a, b, c);
Verilog attributes are not supported for:
• Signal declarations
• Statements
• Port connections
• Expression operators
Verilog Meta Comments
Constraints can also be specified in Verilog code using meta comments. The Verilog
format is the preferred syntax, but the meta comment style is still supported. Use the
following syntax:
// synthesis attribute AttributeName [of] ObjectName [is] AttributeValue
Verilog Meta Comments Examples
// synthesis attribute RLOC of u123 is R11C1.S0
// synthesis attribute HU_SET u1 MY_SET
// synthesis attribute bufg of my_clock is "clk"
Constraints Guide
30 www.xilinx.com UG625 (v. 13.2) July 6, 2011