Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
Schematic Syntax
• Attach to a valid instance
• Attribute Name
HU_SET
• Attribute Values
set_name
VHDL Syntax
Declare the VHDL constraint as follows:
attribute HU_SET: string;
Specify the VHDL constraint as follows:
attribute HU_SET of {component_name | entity_name | label_name} : {component | entity
| label} is "set_name";
For more information about basic VHDL syntax, see VHDL Attributes.
Verilog Syntax
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* HU_SET = "set_name" *)
For more information about basic Verilog syntax, see Verilog Attributes.
UCF and NCF Syntax
INST "instance_name" HU_SET=set_name ;
where
• set_name is the identifier for the set
• set_name must be unique among all the sets in the design
The following statement assigns an instance of the register FF_1 to a set named
heavy_set.
INST "$1I3245/FF_1" HU_SET=heavy_set;
XCF Syntax
MODEL "entity_name" hu_set={yes | no};
BEGIN MODEL "entity_name"
INST "instance_name" hu_set=yes;
END;
Constraints Guide
132 www.xilinx.com UG625 (v. 13.2) July 6, 2011