Xilinx Constraints Guide

Syntax Examples
Chapter 4: Xilinx Constraints
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Schematic Syntax
• Attach to an instance that is a member of a set
• Attribute Name
RLOC_ORIGIN
• Attribute Values
For a list of the constraint values, see the UCF and NCF Syntax section below.
VHDL Syntax
Declare the VHDL constraint as follows:
attribute rloc_origin: string;
Specify the VHDL constraint as follows:
attribute rloc_origin of {component_name |entity_name|label_name} : {component|entity
|label} is “ value”;
For Spartan®-3, Spartan-3A, Spartan-3E, Virtex®-4 and Virtex-5 devices, value is X mYn.
For a list of the constraint values, see the UCF and NCF Syntax section below.
For more information about basic VHDL syntax, see VHDL Attributes.
Verilog Syntax
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* RLOC_ORIGIN = “ value” *)
For Spartan-3, Spartan-3A, Spartan-3E, Virtex-4 and Virtex-5 devices, value is X mYn.
For a list of the constraint values, see the UCF and NCF Syntax section below.
For more information about basic Verilog syntax, see Verilog Attributes.
UCF and NCF Syntax for Architectures Using Slice-Based XY Coordinates
This section applies to Spartan-3, Spartan-3A, Spartan-3E, Virtex-4, and Virtex-5 devices.
RLOC_ORIGIN=X mYn
where
m and n are positive or negative integers (including zero) representing relative X and Y
coordinates, respectively
The following statement specifies that an instantiation of FF1, which is a member of a
set, be placed in the slice at X4Y4 relative to FF1.
INST “/archive/designs/FF1” RLOC_ORIGIN=X4Y4;
For example, if RLOC=X0Y2 for FF1, then the instantiation of FF1 is placed in the slice
that is:
• 0 rows to the right of X4
• 2 rows up from Y4 (X4Y6)
Constraints Guide
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