Xilinx Constraints Guide

Defining I/O Pin Configurations
Chapter 2: Entry Strategies for Xilinx Constraints
This section discusses Defining I/O Pin Configurations and includes:
• Pin Assignment Overview
• Reviewing I/O Pin Data Information
• Pin Assignment
• I/O Planner Documentation
Pin Assignment Overview
I/O Planner can be invoked either as a standalone tool or from within ISE Design Suite.
Invoking I/O Planner standalone can be helpful early in the design process when HDL
sources may not yet be complete. I/O ports can be defined manually within the tool,
or by importing a CSV format spreadsheet or HDL sources. You can define an initial
pinout and export a User Constraints File (UCF) file for use in the ISE Design Suite flow.
A UCF file is required when invoking I/O Planner from within ISE Design Suite. If a
UCF file does not exist, an empty one is created. Creation of I/O ports manually or
by importing a CSV spreadsheet is not enabled when invoking I/O Planner from ISE
Design Suite.
I/O Planner is an I/O pin assignment environment containing many helpful views and
capabilities. You can selectively drag and drop groups of I/O ports onto the device using
a variety of methods. An automatic placement routine is also available. Comprehensive
Design Rule Checks (DRCs) ensure legal pinout definition.
Reviewing I/O Pin Data Information
Data Sheets provide device specifications, including I/O standards. To get device-specific
I/O standard information, see the data sheet for the device you are targeting. A lot of
the data contained in the data sheets is also available inside of the I/O Planner tool. The
types of information available include I/O standards, clock capable pins, internal trace
delays, differential pairs, clock region and I/O bank contents, etc. Information about
I/O related device resources such as global and regional clock buffers, I/O delays and
delay controllers, gigabit transceivers, etc. is also available.
Constraints Guide
UG625 (v. 13.2) July 6, 2011 www.xilinx.com 41