Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
SYSTEM_JITTER (System Jitter)
Architecture Support
Applicable Elements
Propagation Rules
The SYSTEM_JITTER (System Jitter) constraint:
• Specifies the system jitter of the design.
• Depends on design conditions such as:
– the number of flip-flops changing at one time
– the number of I/Os changing
• Applies globally to all clocks in the design.
• Is combined with the INPUT_JITTER keyword on the PERIOD constraint, as well
as any jitter or phase error in the clock network, to generate the Clock Uncertainty
value that is shown in the timing report.
Applies to FPGA devices. Does not apply to CPLD devices.
Applies to the entire design.
Not applicable
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
Values
value is a numerical value. The default is ps.
Schematic Syntax
• Attach to a valid instance
• Attribute Name
SYSTEM_JITTER
• Attribute Values
See Values section above.
VHDL Syntax
Declare the VHDL constraint as follows:
attribute SYSTEM_JITTER: string;
Specify the VHDL constraint as follows:
attribute SYSTEM_JITTER of {component_name | signal_name | entity_name |
label_name}: {component | signal | entity| label} is “value ps”;
For more information about basic VHDL syntax, see VHDL Attributes.
Constraints Guide
272 www.xilinx.com UG625 (v. 13.2) July 6, 2011