Xilinx Constraints Guide

Verilog Syntax
Chapter 4: Xilinx Constraints
Place the Verilog constraint immediately before the module or instantiation.
Specify the Verilog constraint as follows:
(* KEEP = “{TRUE|FALSE |SOFT}” *)
For more information about basic Verilog syntax, see Verilog Attributes.
UCF and NCF Syntax
INST “instance_name” KEEP={TRUE|FALSE};
The following statement ensures that the net $SIG_0 remains visible.
NET “$1I3245/$SIG_0” KEEP;
XCF Syntax
BEGIN MODEL “entity_name”
NET “signal_name” keep={yes|no|true|false};
END;
In an XST Constraint File (XCF) file, the value of the KEEP constraint may optionally
be enclosed in double quotes. For the SOFT value, this becomes mandatory, as shown
below:
BEGIN MODEL “entity_name”
NET “signal_name” keep=”soft”;
END;
Constraints Guide
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