Xilinx Constraints Guide

Chapter 4: Xilinx Constraints
Internal Vref Bank (INTERNAL_VREF_BANK)
Architecture Support
Applicable Elements
Propagation Rules
Syntax
The Internal Vref Bank (INTERNAL_VREF_BANK) constraint:
• Provides a means of assigning a voltage value to the internal Vref feature for a
given IO bank.
• Is useful for freeing the Vref pins of IO banks from their function of providing
a voltage reference. By using the internal Vref on an IO bank, the Vref pins can
assume an alternative use.
Applies to Virtex®-6, Kintex-7, and Virtex®-7 devices
This constraint is a global CONFIG constraint and is not attached to any instance or
signal name.
Applies to IOs in the specified bank for the entire design
The following sections show the syntax for this constraint.
Syntax Examples
The following examples show how to use this constraint with particular tools or
methods. If a tool or method is not listed, you cannot use this constraint with it.
UCF and NCF Syntax
CONFIG INTERNAL_VREF_BANKn=v;
where
• n is the number of the bank
• v is the target voltage value (0.0, 0.6, 0.675, 0.75, 0.9, 1.1, 1.25)
Example
CONFIG INTERNAL_VREF_BANK5=1.1;
Constraints Guide
140 www.xilinx.com UG625 (v. 13.2) July 6, 2011